1 /*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c.h>
18 #include <linux/gpio.h>
19 #include <linux/leds.h>
20 #include <linux/input.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/spi/flash.h>
24 #include <linux/spi/spi.h>
25 #include <linux/mfd/mc13892.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/regulator/consumer.h>
28
29 #include <mach/common.h>
30 #include <mach/hardware.h>
31 #include <mach/iomux-mx51.h>
32
33 #include <linux/usb/otg.h>
34 #include <linux/usb/ulpi.h>
35 #include <mach/ulpi.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41
42 #include "devices-imx51.h"
43 #include "efika.h"
44 #include "cpu_op-mx51.h"
45
46 #define MX51_USB_CTRL_1_OFFSET 0x10
47 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
49
50 #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
51 #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
52
53 #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
54 #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
55
56 #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
57
58 static iomux_v3_cfg_t mx51efika_pads[] = {
59 /* UART1 */
60 MX51_PAD_UART1_RXD__UART1_RXD,
61 MX51_PAD_UART1_TXD__UART1_TXD,
62 MX51_PAD_UART1_RTS__UART1_RTS,
63 MX51_PAD_UART1_CTS__UART1_CTS,
64
65 /* SD 1 */
66 MX51_PAD_SD1_CMD__SD1_CMD,
67 MX51_PAD_SD1_CLK__SD1_CLK,
68 MX51_PAD_SD1_DATA0__SD1_DATA0,
69 MX51_PAD_SD1_DATA1__SD1_DATA1,
70 MX51_PAD_SD1_DATA2__SD1_DATA2,
71 MX51_PAD_SD1_DATA3__SD1_DATA3,
72
73 /* SD 2 */
74 MX51_PAD_SD2_CMD__SD2_CMD,
75 MX51_PAD_SD2_CLK__SD2_CLK,
76 MX51_PAD_SD2_DATA0__SD2_DATA0,
77 MX51_PAD_SD2_DATA1__SD2_DATA1,
78 MX51_PAD_SD2_DATA2__SD2_DATA2,
79 MX51_PAD_SD2_DATA3__SD2_DATA3,
80
81 /* SD/MMC WP/CD */
82 MX51_PAD_GPIO1_0__SD1_CD,
83 MX51_PAD_GPIO1_1__SD1_WP,
84 MX51_PAD_GPIO1_7__SD2_WP,
85 MX51_PAD_GPIO1_8__SD2_CD,
86
87 /* spi */
88 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
89 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
90 MX51_PAD_CSPI1_SS0__GPIO4_24,
91 MX51_PAD_CSPI1_SS1__GPIO4_25,
92 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
93 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
94 MX51_PAD_GPIO1_6__GPIO1_6,
95
96 /* USB HOST1 */
97 MX51_PAD_USBH1_CLK__USBH1_CLK,
98 MX51_PAD_USBH1_DIR__USBH1_DIR,
99 MX51_PAD_USBH1_NXT__USBH1_NXT,
100 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
101 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
102 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
103 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
104 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
105 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
106 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
107 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
108
109 /* USB HUB RESET */
110 MX51_PAD_GPIO1_5__GPIO1_5,
111
112 /* WLAN */
113 MX51_PAD_EIM_A22__GPIO2_16,
114 MX51_PAD_EIM_A16__GPIO2_10,
115
116 /* USB PHY RESET */
117 MX51_PAD_EIM_D27__GPIO2_9,
118 };
119
120 /* Serial ports */
121 static const struct imxuart_platform_data uart_pdata = {
122 .flags = IMXUART_HAVE_RTSCTS,
123 };
124
125 /* This function is board specific as the bit mask for the plldiv will also
126 * be different for other Freescale SoCs, thus a common bitmask is not
127 * possible and cannot get place in /plat-mxc/ehci.c.
128 */
initialize_otg_port(struct platform_device * pdev)129 static int initialize_otg_port(struct platform_device *pdev)
130 {
131 u32 v;
132 void __iomem *usb_base;
133 void __iomem *usbother_base;
134 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
135 if (!usb_base)
136 return -ENOMEM;
137 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
138
139 /* Set the PHY clock to 19.2MHz */
140 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
141 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
142 v |= MX51_USB_PLL_DIV_19_2_MHZ;
143 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
144 iounmap(usb_base);
145
146 mdelay(10);
147
148 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
149 }
150
151 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
152 .init = initialize_otg_port,
153 .portsc = MXC_EHCI_UTMI_16BIT,
154 };
155
initialize_usbh1_port(struct platform_device * pdev)156 static int initialize_usbh1_port(struct platform_device *pdev)
157 {
158 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
159 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
160 u32 v;
161 void __iomem *usb_base;
162 void __iomem *socregs_base;
163
164 mxc_iomux_v3_setup_pad(usbh1gpio);
165 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
166 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
167 msleep(1);
168 gpio_set_value(EFIKAMX_USBH1_STP, 1);
169 msleep(1);
170
171 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
172 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
173
174 /* The clock for the USBH1 ULPI port will come externally */
175 /* from the PHY. */
176 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
177 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
178 socregs_base + MX51_USB_CTRL_1_OFFSET);
179
180 iounmap(usb_base);
181
182 gpio_free(EFIKAMX_USBH1_STP);
183 mxc_iomux_v3_setup_pad(usbh1stp);
184
185 mdelay(10);
186
187 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
188 }
189
190 static struct mxc_usbh_platform_data usbh1_config __initdata = {
191 .init = initialize_usbh1_port,
192 .portsc = MXC_EHCI_MODE_ULPI,
193 };
194
mx51_efika_hubreset(void)195 static void mx51_efika_hubreset(void)
196 {
197 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
198 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
199 msleep(1);
200 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
201 msleep(1);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
203 }
204
mx51_efika_usb(void)205 static void __init mx51_efika_usb(void)
206 {
207 mx51_efika_hubreset();
208
209 /* pulling it low, means no USB at all... */
210 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
211 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
212 msleep(1);
213 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
214
215 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
216 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
217
218 imx51_add_mxc_ehci_otg(&dr_utmi_config);
219 if (usbh1_config.otg)
220 imx51_add_mxc_ehci_hs(1, &usbh1_config);
221 }
222
223 static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
224 {
225 .name = "u-boot",
226 .offset = 0,
227 .size = SZ_256K,
228 },
229 {
230 .name = "config",
231 .offset = MTDPART_OFS_APPEND,
232 .size = SZ_64K,
233 },
234 };
235
236 static struct flash_platform_data mx51_efika_spi_flash_data = {
237 .name = "spi_flash",
238 .parts = mx51_efika_spi_nor_partitions,
239 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
240 .type = "sst25vf032b",
241 };
242
243 static struct regulator_consumer_supply sw1_consumers[] = {
244 {
245 .supply = "cpu_vcc",
246 }
247 };
248
249 static struct regulator_consumer_supply vdig_consumers[] = {
250 /* sgtl5000 */
251 REGULATOR_SUPPLY("VDDA", "1-000a"),
252 REGULATOR_SUPPLY("VDDD", "1-000a"),
253 };
254
255 static struct regulator_consumer_supply vvideo_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDIO", "1-000a"),
258 };
259
260 static struct regulator_consumer_supply vsd_consumers[] = {
261 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
262 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
263 };
264
265 static struct regulator_consumer_supply pwgt1_consumer[] = {
266 {
267 .supply = "pwgt1",
268 }
269 };
270
271 static struct regulator_consumer_supply pwgt2_consumer[] = {
272 {
273 .supply = "pwgt2",
274 }
275 };
276
277 static struct regulator_consumer_supply coincell_consumer[] = {
278 {
279 .supply = "coincell",
280 }
281 };
282
283 static struct regulator_init_data sw1_init = {
284 .constraints = {
285 .name = "SW1",
286 .min_uV = 600000,
287 .max_uV = 1375000,
288 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
289 .valid_modes_mask = 0,
290 .always_on = 1,
291 .boot_on = 1,
292 .state_mem = {
293 .uV = 850000,
294 .mode = REGULATOR_MODE_NORMAL,
295 .enabled = 1,
296 },
297 },
298 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
299 .consumer_supplies = sw1_consumers,
300 };
301
302 static struct regulator_init_data sw2_init = {
303 .constraints = {
304 .name = "SW2",
305 .min_uV = 900000,
306 .max_uV = 1850000,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
308 .always_on = 1,
309 .boot_on = 1,
310 .state_mem = {
311 .uV = 950000,
312 .mode = REGULATOR_MODE_NORMAL,
313 .enabled = 1,
314 },
315 }
316 };
317
318 static struct regulator_init_data sw3_init = {
319 .constraints = {
320 .name = "SW3",
321 .min_uV = 1100000,
322 .max_uV = 1850000,
323 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
324 .always_on = 1,
325 .boot_on = 1,
326 }
327 };
328
329 static struct regulator_init_data sw4_init = {
330 .constraints = {
331 .name = "SW4",
332 .min_uV = 1100000,
333 .max_uV = 1850000,
334 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
335 .always_on = 1,
336 .boot_on = 1,
337 }
338 };
339
340 static struct regulator_init_data viohi_init = {
341 .constraints = {
342 .name = "VIOHI",
343 .boot_on = 1,
344 .always_on = 1,
345 }
346 };
347
348 static struct regulator_init_data vusb_init = {
349 .constraints = {
350 .name = "VUSB",
351 .boot_on = 1,
352 .always_on = 1,
353 }
354 };
355
356 static struct regulator_init_data swbst_init = {
357 .constraints = {
358 .name = "SWBST",
359 }
360 };
361
362 static struct regulator_init_data vdig_init = {
363 .constraints = {
364 .name = "VDIG",
365 .min_uV = 1050000,
366 .max_uV = 1800000,
367 .valid_ops_mask =
368 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
369 .boot_on = 1,
370 .always_on = 1,
371 },
372 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
373 .consumer_supplies = vdig_consumers,
374 };
375
376 static struct regulator_init_data vpll_init = {
377 .constraints = {
378 .name = "VPLL",
379 .min_uV = 1050000,
380 .max_uV = 1800000,
381 .valid_ops_mask =
382 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
383 .boot_on = 1,
384 .always_on = 1,
385 }
386 };
387
388 static struct regulator_init_data vusb2_init = {
389 .constraints = {
390 .name = "VUSB2",
391 .min_uV = 2400000,
392 .max_uV = 2775000,
393 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
394 .boot_on = 1,
395 .always_on = 1,
396 }
397 };
398
399 static struct regulator_init_data vvideo_init = {
400 .constraints = {
401 .name = "VVIDEO",
402 .min_uV = 2775000,
403 .max_uV = 2775000,
404 .valid_ops_mask =
405 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
406 .boot_on = 1,
407 .apply_uV = 1,
408 },
409 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
410 .consumer_supplies = vvideo_consumers,
411 };
412
413 static struct regulator_init_data vaudio_init = {
414 .constraints = {
415 .name = "VAUDIO",
416 .min_uV = 2300000,
417 .max_uV = 3000000,
418 .valid_ops_mask =
419 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
420 .boot_on = 1,
421 }
422 };
423
424 static struct regulator_init_data vsd_init = {
425 .constraints = {
426 .name = "VSD",
427 .min_uV = 1800000,
428 .max_uV = 3150000,
429 .valid_ops_mask =
430 REGULATOR_CHANGE_VOLTAGE,
431 .boot_on = 1,
432 },
433 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
434 .consumer_supplies = vsd_consumers,
435 };
436
437 static struct regulator_init_data vcam_init = {
438 .constraints = {
439 .name = "VCAM",
440 .min_uV = 2500000,
441 .max_uV = 3000000,
442 .valid_ops_mask =
443 REGULATOR_CHANGE_VOLTAGE |
444 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
445 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
446 .boot_on = 1,
447 }
448 };
449
450 static struct regulator_init_data vgen1_init = {
451 .constraints = {
452 .name = "VGEN1",
453 .min_uV = 1200000,
454 .max_uV = 3150000,
455 .valid_ops_mask =
456 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
457 .boot_on = 1,
458 .always_on = 1,
459 }
460 };
461
462 static struct regulator_init_data vgen2_init = {
463 .constraints = {
464 .name = "VGEN2",
465 .min_uV = 1200000,
466 .max_uV = 3150000,
467 .valid_ops_mask =
468 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
469 .boot_on = 1,
470 .always_on = 1,
471 }
472 };
473
474 static struct regulator_init_data vgen3_init = {
475 .constraints = {
476 .name = "VGEN3",
477 .min_uV = 1800000,
478 .max_uV = 2900000,
479 .valid_ops_mask =
480 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
481 .boot_on = 1,
482 .always_on = 1,
483 }
484 };
485
486 static struct regulator_init_data gpo1_init = {
487 .constraints = {
488 .name = "GPO1",
489 }
490 };
491
492 static struct regulator_init_data gpo2_init = {
493 .constraints = {
494 .name = "GPO2",
495 }
496 };
497
498 static struct regulator_init_data gpo3_init = {
499 .constraints = {
500 .name = "GPO3",
501 }
502 };
503
504 static struct regulator_init_data gpo4_init = {
505 .constraints = {
506 .name = "GPO4",
507 }
508 };
509
510 static struct regulator_init_data pwgt1_init = {
511 .constraints = {
512 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
513 .boot_on = 1,
514 },
515 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
516 .consumer_supplies = pwgt1_consumer,
517 };
518
519 static struct regulator_init_data pwgt2_init = {
520 .constraints = {
521 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
522 .boot_on = 1,
523 },
524 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
525 .consumer_supplies = pwgt2_consumer,
526 };
527
528 static struct regulator_init_data vcoincell_init = {
529 .constraints = {
530 .name = "COINCELL",
531 .min_uV = 3000000,
532 .max_uV = 3000000,
533 .valid_ops_mask =
534 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
535 },
536 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
537 .consumer_supplies = coincell_consumer,
538 };
539
540 static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
541 { .id = MC13892_SW1, .init_data = &sw1_init },
542 { .id = MC13892_SW2, .init_data = &sw2_init },
543 { .id = MC13892_SW3, .init_data = &sw3_init },
544 { .id = MC13892_SW4, .init_data = &sw4_init },
545 { .id = MC13892_SWBST, .init_data = &swbst_init },
546 { .id = MC13892_VIOHI, .init_data = &viohi_init },
547 { .id = MC13892_VPLL, .init_data = &vpll_init },
548 { .id = MC13892_VDIG, .init_data = &vdig_init },
549 { .id = MC13892_VSD, .init_data = &vsd_init },
550 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
551 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
552 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
553 { .id = MC13892_VCAM, .init_data = &vcam_init },
554 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
555 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
556 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
557 { .id = MC13892_VUSB, .init_data = &vusb_init },
558 { .id = MC13892_GPO1, .init_data = &gpo1_init },
559 { .id = MC13892_GPO2, .init_data = &gpo2_init },
560 { .id = MC13892_GPO3, .init_data = &gpo3_init },
561 { .id = MC13892_GPO4, .init_data = &gpo4_init },
562 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
563 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
564 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
565 };
566
567 static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
568 .flags = MC13XXX_USE_RTC,
569 .regulators = {
570 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
571 .regulators = mx51_efika_regulators,
572 },
573 };
574
575 static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
576 {
577 .modalias = "m25p80",
578 .max_speed_hz = 25000000,
579 .bus_num = 0,
580 .chip_select = 1,
581 .platform_data = &mx51_efika_spi_flash_data,
582 .irq = -1,
583 },
584 {
585 .modalias = "mc13892",
586 .max_speed_hz = 1000000,
587 .bus_num = 0,
588 .chip_select = 0,
589 .platform_data = &mx51_efika_mc13892_data,
590 .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
591 },
592 };
593
594 static int mx51_efika_spi_cs[] = {
595 EFIKAMX_SPI_CS0,
596 EFIKAMX_SPI_CS1,
597 };
598
599 static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
600 .chipselect = mx51_efika_spi_cs,
601 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
602 };
603
efika_board_common_init(void)604 void __init efika_board_common_init(void)
605 {
606 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
607 ARRAY_SIZE(mx51efika_pads));
608 imx51_add_imx_uart(0, &uart_pdata);
609 mx51_efika_usb();
610
611 /* FIXME: comes from original code. check this. */
612 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
613 sw2_init.constraints.state_mem.uV = 1100000;
614 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
615 sw2_init.constraints.state_mem.uV = 1250000;
616 sw1_init.constraints.state_mem.uV = 1000000;
617 }
618 if (machine_is_mx51_efikasb())
619 vgen1_init.constraints.max_uV = 1200000;
620
621 gpio_request(EFIKAMX_PMIC, "pmic irq");
622 gpio_direction_input(EFIKAMX_PMIC);
623 spi_register_board_info(mx51_efika_spi_board_info,
624 ARRAY_SIZE(mx51_efika_spi_board_info));
625 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
626
627 imx51_add_pata_imx();
628
629 #if defined(CONFIG_CPU_FREQ_IMX)
630 get_cpu_op = mx51_get_cpu_op;
631 #endif
632 }
633