1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41
42 /* General customization:
43 */
44
45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46
47 #define DRIVER_NAME "i915"
48 #define DRIVER_DESC "Intel Graphics"
49 #define DRIVER_DATE "20080730"
50
51 enum pipe {
52 PIPE_A = 0,
53 PIPE_B,
54 PIPE_C,
55 I915_MAX_PIPES
56 };
57 #define pipe_name(p) ((p) + 'A')
58
59 enum plane {
60 PLANE_A = 0,
61 PLANE_B,
62 PLANE_C,
63 };
64 #define plane_name(p) ((p) + 'A')
65
66 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67
68 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
69
70 /* Interface history:
71 *
72 * 1.1: Original.
73 * 1.2: Add Power Management
74 * 1.3: Add vblank support
75 * 1.4: Fix cmdbuffer path, add heap destroy
76 * 1.5: Add vblank pipe configuration
77 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
78 * - Support vertical blank on secondary display pipe
79 */
80 #define DRIVER_MAJOR 1
81 #define DRIVER_MINOR 6
82 #define DRIVER_PATCHLEVEL 0
83
84 #define WATCH_COHERENCY 0
85 #define WATCH_LISTS 0
86
87 #define I915_GEM_PHYS_CURSOR_0 1
88 #define I915_GEM_PHYS_CURSOR_1 2
89 #define I915_GEM_PHYS_OVERLAY_REGS 3
90 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91
92 struct drm_i915_gem_phys_object {
93 int id;
94 struct page **page_list;
95 drm_dma_handle_t *handle;
96 struct drm_i915_gem_object *cur_obj;
97 };
98
99 struct mem_block {
100 struct mem_block *next;
101 struct mem_block *prev;
102 int start;
103 int size;
104 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
105 };
106
107 struct opregion_header;
108 struct opregion_acpi;
109 struct opregion_swsci;
110 struct opregion_asle;
111 struct drm_i915_private;
112
113 struct intel_opregion {
114 struct opregion_header *header;
115 struct opregion_acpi *acpi;
116 struct opregion_swsci *swsci;
117 struct opregion_asle *asle;
118 void *vbt;
119 u32 __iomem *lid_state;
120 };
121 #define OPREGION_SIZE (8*1024)
122
123 struct intel_overlay;
124 struct intel_overlay_error_state;
125
126 struct drm_i915_master_private {
127 drm_local_map_t *sarea;
128 struct _drm_i915_sarea *sarea_priv;
129 };
130 #define I915_FENCE_REG_NONE -1
131 #define I915_MAX_NUM_FENCES 16
132 /* 16 fences + sign bit for FENCE_REG_NONE */
133 #define I915_MAX_NUM_FENCE_BITS 5
134
135 struct drm_i915_fence_reg {
136 struct list_head lru_list;
137 struct drm_i915_gem_object *obj;
138 uint32_t setup_seqno;
139 int pin_count;
140 };
141
142 struct sdvo_device_mapping {
143 u8 initialized;
144 u8 dvo_port;
145 u8 slave_addr;
146 u8 dvo_wiring;
147 u8 i2c_pin;
148 u8 ddc_pin;
149 };
150
151 struct intel_display_error_state;
152
153 struct drm_i915_error_state {
154 u32 eir;
155 u32 pgtbl_er;
156 u32 pipestat[I915_MAX_PIPES];
157 u32 tail[I915_NUM_RINGS];
158 u32 head[I915_NUM_RINGS];
159 u32 ipeir[I915_NUM_RINGS];
160 u32 ipehr[I915_NUM_RINGS];
161 u32 instdone[I915_NUM_RINGS];
162 u32 acthd[I915_NUM_RINGS];
163 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
164 /* our own tracking of ring head and tail */
165 u32 cpu_ring_head[I915_NUM_RINGS];
166 u32 cpu_ring_tail[I915_NUM_RINGS];
167 u32 error; /* gen6+ */
168 u32 instpm[I915_NUM_RINGS];
169 u32 instps[I915_NUM_RINGS];
170 u32 instdone1;
171 u32 seqno[I915_NUM_RINGS];
172 u64 bbaddr;
173 u32 fault_reg[I915_NUM_RINGS];
174 u32 done_reg;
175 u32 faddr[I915_NUM_RINGS];
176 u64 fence[I915_MAX_NUM_FENCES];
177 struct timeval time;
178 struct drm_i915_error_ring {
179 struct drm_i915_error_object {
180 int page_count;
181 u32 gtt_offset;
182 u32 *pages[0];
183 } *ringbuffer, *batchbuffer;
184 struct drm_i915_error_request {
185 long jiffies;
186 u32 seqno;
187 u32 tail;
188 } *requests;
189 int num_requests;
190 } ring[I915_NUM_RINGS];
191 struct drm_i915_error_buffer {
192 u32 size;
193 u32 name;
194 u32 seqno;
195 u32 gtt_offset;
196 u32 read_domains;
197 u32 write_domain;
198 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
199 s32 pinned:2;
200 u32 tiling:2;
201 u32 dirty:1;
202 u32 purgeable:1;
203 s32 ring:4;
204 u32 cache_level:2;
205 } *active_bo, *pinned_bo;
206 u32 active_bo_count, pinned_bo_count;
207 struct intel_overlay_error_state *overlay;
208 struct intel_display_error_state *display;
209 };
210
211 struct drm_i915_display_funcs {
212 void (*dpms)(struct drm_crtc *crtc, int mode);
213 bool (*fbc_enabled)(struct drm_device *dev);
214 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
215 void (*disable_fbc)(struct drm_device *dev);
216 int (*get_display_clock_speed)(struct drm_device *dev);
217 int (*get_fifo_size)(struct drm_device *dev, int plane);
218 void (*update_wm)(struct drm_device *dev);
219 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
220 uint32_t sprite_width, int pixel_size);
221 int (*crtc_mode_set)(struct drm_crtc *crtc,
222 struct drm_display_mode *mode,
223 struct drm_display_mode *adjusted_mode,
224 int x, int y,
225 struct drm_framebuffer *old_fb);
226 void (*write_eld)(struct drm_connector *connector,
227 struct drm_crtc *crtc);
228 void (*fdi_link_train)(struct drm_crtc *crtc);
229 void (*init_clock_gating)(struct drm_device *dev);
230 void (*init_pch_clock_gating)(struct drm_device *dev);
231 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
232 struct drm_framebuffer *fb,
233 struct drm_i915_gem_object *obj);
234 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
235 int x, int y);
236 void (*force_wake_get)(struct drm_i915_private *dev_priv);
237 void (*force_wake_put)(struct drm_i915_private *dev_priv);
238 /* clock updates for mode set */
239 /* cursor updates */
240 /* render clock increase/decrease */
241 /* display clock increase/decrease */
242 /* pll clock increase/decrease */
243 };
244
245 struct intel_device_info {
246 u8 gen;
247 u8 is_mobile:1;
248 u8 is_i85x:1;
249 u8 is_i915g:1;
250 u8 is_i945gm:1;
251 u8 is_g33:1;
252 u8 need_gfx_hws:1;
253 u8 is_g4x:1;
254 u8 is_pineview:1;
255 u8 is_broadwater:1;
256 u8 is_crestline:1;
257 u8 is_ivybridge:1;
258 u8 has_force_wake:1;
259 u8 has_fbc:1;
260 u8 has_pipe_cxsr:1;
261 u8 has_hotplug:1;
262 u8 cursor_needs_physical:1;
263 u8 has_overlay:1;
264 u8 overlay_needs_physical:1;
265 u8 supports_tv:1;
266 u8 has_bsd_ring:1;
267 u8 has_blt_ring:1;
268 u8 has_llc:1;
269 };
270
271 #define I915_PPGTT_PD_ENTRIES 512
272 #define I915_PPGTT_PT_ENTRIES 1024
273 struct i915_hw_ppgtt {
274 unsigned num_pd_entries;
275 struct page **pt_pages;
276 uint32_t pd_offset;
277 dma_addr_t *pt_dma_addr;
278 dma_addr_t scratch_page_dma_addr;
279 };
280
281 enum no_fbc_reason {
282 FBC_NO_OUTPUT, /* no outputs enabled to compress */
283 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
284 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
285 FBC_MODE_TOO_LARGE, /* mode too large for compression */
286 FBC_BAD_PLANE, /* fbc not supported on plane */
287 FBC_NOT_TILED, /* buffer not tiled */
288 FBC_MULTIPLE_PIPES, /* more than one pipe active */
289 FBC_MODULE_PARAM,
290 };
291
292 enum intel_pch {
293 PCH_IBX, /* Ibexpeak PCH */
294 PCH_CPT, /* Cougarpoint PCH */
295 };
296
297 #define QUIRK_PIPEA_FORCE (1<<0)
298 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
299 #define QUIRK_NO_PCH_PWM_ENABLE (1<<2)
300
301 struct intel_fbdev;
302 struct intel_fbc_work;
303
304 struct intel_gmbus {
305 struct i2c_adapter adapter;
306 bool force_bit;
307 bool has_gpio;
308 u32 reg0;
309 u32 gpio_reg;
310 struct i2c_algo_bit_data bit_algo;
311 struct drm_i915_private *dev_priv;
312 };
313
314 typedef struct drm_i915_private {
315 struct drm_device *dev;
316
317 const struct intel_device_info *info;
318
319 int has_gem;
320 int relative_constants_mode;
321
322 void __iomem *regs;
323 /** gt_fifo_count and the subsequent register write are synchronized
324 * with dev->struct_mutex. */
325 unsigned gt_fifo_count;
326 /** forcewake_count is protected by gt_lock */
327 unsigned forcewake_count;
328 /** gt_lock is also taken in irq contexts. */
329 struct spinlock gt_lock;
330
331 struct intel_gmbus *gmbus;
332
333 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
334 * controller on different i2c buses. */
335 struct mutex gmbus_mutex;
336
337 struct pci_dev *bridge_dev;
338 struct intel_ring_buffer ring[I915_NUM_RINGS];
339 uint32_t next_seqno;
340
341 drm_dma_handle_t *status_page_dmah;
342 uint32_t counter;
343 drm_local_map_t hws_map;
344 struct drm_i915_gem_object *pwrctx;
345 struct drm_i915_gem_object *renderctx;
346
347 struct resource mch_res;
348
349 unsigned int cpp;
350 int back_offset;
351 int front_offset;
352 int current_page;
353 int page_flipping;
354
355 atomic_t irq_received;
356
357 /* protects the irq masks */
358 spinlock_t irq_lock;
359 /** Cached value of IMR to avoid reads in updating the bitfield */
360 u32 pipestat[2];
361 u32 irq_mask;
362 u32 gt_irq_mask;
363 u32 pch_irq_mask;
364
365 u32 hotplug_supported_mask;
366 struct work_struct hotplug_work;
367
368 int tex_lru_log_granularity;
369 int allow_batchbuffer;
370 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
371 int vblank_pipe;
372 int num_pipe;
373
374 /* For hangcheck timer */
375 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
376 struct timer_list hangcheck_timer;
377 int hangcheck_count;
378 uint32_t last_acthd;
379 uint32_t last_acthd_bsd;
380 uint32_t last_acthd_blt;
381 uint32_t last_instdone;
382 uint32_t last_instdone1;
383
384 unsigned long cfb_size;
385 unsigned int cfb_fb;
386 enum plane cfb_plane;
387 int cfb_y;
388 struct intel_fbc_work *fbc_work;
389
390 struct intel_opregion opregion;
391
392 /* overlay */
393 struct intel_overlay *overlay;
394 bool sprite_scaling_enabled;
395
396 /* LVDS info */
397 int backlight_level; /* restore backlight to this value */
398 bool backlight_enabled;
399 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
400 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
401
402 /* Feature bits from the VBIOS */
403 unsigned int int_tv_support:1;
404 unsigned int lvds_dither:1;
405 unsigned int lvds_vbt:1;
406 unsigned int int_crt_support:1;
407 unsigned int lvds_use_ssc:1;
408 unsigned int display_clock_mode:1;
409 int lvds_ssc_freq;
410 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
411 unsigned int lvds_val; /* used for checking LVDS channel mode */
412 struct {
413 int rate;
414 int lanes;
415 int preemphasis;
416 int vswing;
417
418 bool initialized;
419 bool support;
420 int bpp;
421 struct edp_power_seq pps;
422 } edp;
423 bool no_aux_handshake;
424
425 struct notifier_block lid_notifier;
426
427 int crt_ddc_pin;
428 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
429 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
430 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
431
432 unsigned int fsb_freq, mem_freq, is_ddr3;
433
434 spinlock_t error_lock;
435 struct drm_i915_error_state *first_error;
436 struct work_struct error_work;
437 struct completion error_completion;
438 struct workqueue_struct *wq;
439
440 /* Display functions */
441 struct drm_i915_display_funcs display;
442
443 /* PCH chipset type */
444 enum intel_pch pch_type;
445
446 unsigned long quirks;
447
448 /* Register state */
449 bool modeset_on_lid;
450 u8 saveLBB;
451 u32 saveDSPACNTR;
452 u32 saveDSPBCNTR;
453 u32 saveDSPARB;
454 u32 saveHWS;
455 u32 savePIPEACONF;
456 u32 savePIPEBCONF;
457 u32 savePIPEASRC;
458 u32 savePIPEBSRC;
459 u32 saveFPA0;
460 u32 saveFPA1;
461 u32 saveDPLL_A;
462 u32 saveDPLL_A_MD;
463 u32 saveHTOTAL_A;
464 u32 saveHBLANK_A;
465 u32 saveHSYNC_A;
466 u32 saveVTOTAL_A;
467 u32 saveVBLANK_A;
468 u32 saveVSYNC_A;
469 u32 saveBCLRPAT_A;
470 u32 saveTRANSACONF;
471 u32 saveTRANS_HTOTAL_A;
472 u32 saveTRANS_HBLANK_A;
473 u32 saveTRANS_HSYNC_A;
474 u32 saveTRANS_VTOTAL_A;
475 u32 saveTRANS_VBLANK_A;
476 u32 saveTRANS_VSYNC_A;
477 u32 savePIPEASTAT;
478 u32 saveDSPASTRIDE;
479 u32 saveDSPASIZE;
480 u32 saveDSPAPOS;
481 u32 saveDSPAADDR;
482 u32 saveDSPASURF;
483 u32 saveDSPATILEOFF;
484 u32 savePFIT_PGM_RATIOS;
485 u32 saveBLC_HIST_CTL;
486 u32 saveBLC_PWM_CTL;
487 u32 saveBLC_PWM_CTL2;
488 u32 saveBLC_CPU_PWM_CTL;
489 u32 saveBLC_CPU_PWM_CTL2;
490 u32 saveFPB0;
491 u32 saveFPB1;
492 u32 saveDPLL_B;
493 u32 saveDPLL_B_MD;
494 u32 saveHTOTAL_B;
495 u32 saveHBLANK_B;
496 u32 saveHSYNC_B;
497 u32 saveVTOTAL_B;
498 u32 saveVBLANK_B;
499 u32 saveVSYNC_B;
500 u32 saveBCLRPAT_B;
501 u32 saveTRANSBCONF;
502 u32 saveTRANS_HTOTAL_B;
503 u32 saveTRANS_HBLANK_B;
504 u32 saveTRANS_HSYNC_B;
505 u32 saveTRANS_VTOTAL_B;
506 u32 saveTRANS_VBLANK_B;
507 u32 saveTRANS_VSYNC_B;
508 u32 savePIPEBSTAT;
509 u32 saveDSPBSTRIDE;
510 u32 saveDSPBSIZE;
511 u32 saveDSPBPOS;
512 u32 saveDSPBADDR;
513 u32 saveDSPBSURF;
514 u32 saveDSPBTILEOFF;
515 u32 saveVGA0;
516 u32 saveVGA1;
517 u32 saveVGA_PD;
518 u32 saveVGACNTRL;
519 u32 saveADPA;
520 u32 saveLVDS;
521 u32 savePP_ON_DELAYS;
522 u32 savePP_OFF_DELAYS;
523 u32 saveDVOA;
524 u32 saveDVOB;
525 u32 saveDVOC;
526 u32 savePP_ON;
527 u32 savePP_OFF;
528 u32 savePP_CONTROL;
529 u32 savePP_DIVISOR;
530 u32 savePFIT_CONTROL;
531 u32 save_palette_a[256];
532 u32 save_palette_b[256];
533 u32 saveDPFC_CB_BASE;
534 u32 saveFBC_CFB_BASE;
535 u32 saveFBC_LL_BASE;
536 u32 saveFBC_CONTROL;
537 u32 saveFBC_CONTROL2;
538 u32 saveIER;
539 u32 saveIIR;
540 u32 saveIMR;
541 u32 saveDEIER;
542 u32 saveDEIMR;
543 u32 saveGTIER;
544 u32 saveGTIMR;
545 u32 saveFDI_RXA_IMR;
546 u32 saveFDI_RXB_IMR;
547 u32 saveCACHE_MODE_0;
548 u32 saveMI_ARB_STATE;
549 u32 saveSWF0[16];
550 u32 saveSWF1[16];
551 u32 saveSWF2[3];
552 u8 saveMSR;
553 u8 saveSR[8];
554 u8 saveGR[25];
555 u8 saveAR_INDEX;
556 u8 saveAR[21];
557 u8 saveDACMASK;
558 u8 saveCR[37];
559 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
560 u32 saveCURACNTR;
561 u32 saveCURAPOS;
562 u32 saveCURABASE;
563 u32 saveCURBCNTR;
564 u32 saveCURBPOS;
565 u32 saveCURBBASE;
566 u32 saveCURSIZE;
567 u32 saveDP_B;
568 u32 saveDP_C;
569 u32 saveDP_D;
570 u32 savePIPEA_GMCH_DATA_M;
571 u32 savePIPEB_GMCH_DATA_M;
572 u32 savePIPEA_GMCH_DATA_N;
573 u32 savePIPEB_GMCH_DATA_N;
574 u32 savePIPEA_DP_LINK_M;
575 u32 savePIPEB_DP_LINK_M;
576 u32 savePIPEA_DP_LINK_N;
577 u32 savePIPEB_DP_LINK_N;
578 u32 saveFDI_RXA_CTL;
579 u32 saveFDI_TXA_CTL;
580 u32 saveFDI_RXB_CTL;
581 u32 saveFDI_TXB_CTL;
582 u32 savePFA_CTL_1;
583 u32 savePFB_CTL_1;
584 u32 savePFA_WIN_SZ;
585 u32 savePFB_WIN_SZ;
586 u32 savePFA_WIN_POS;
587 u32 savePFB_WIN_POS;
588 u32 savePCH_DREF_CONTROL;
589 u32 saveDISP_ARB_CTL;
590 u32 savePIPEA_DATA_M1;
591 u32 savePIPEA_DATA_N1;
592 u32 savePIPEA_LINK_M1;
593 u32 savePIPEA_LINK_N1;
594 u32 savePIPEB_DATA_M1;
595 u32 savePIPEB_DATA_N1;
596 u32 savePIPEB_LINK_M1;
597 u32 savePIPEB_LINK_N1;
598 u32 saveMCHBAR_RENDER_STANDBY;
599 u32 savePCH_PORT_HOTPLUG;
600
601 struct {
602 /** Bridge to intel-gtt-ko */
603 const struct intel_gtt *gtt;
604 /** Memory allocator for GTT stolen memory */
605 struct drm_mm stolen;
606 /** Memory allocator for GTT */
607 struct drm_mm gtt_space;
608 /** List of all objects in gtt_space. Used to restore gtt
609 * mappings on resume */
610 struct list_head gtt_list;
611
612 /** Usable portion of the GTT for GEM */
613 unsigned long gtt_start;
614 unsigned long gtt_mappable_end;
615 unsigned long gtt_end;
616
617 struct io_mapping *gtt_mapping;
618 int gtt_mtrr;
619
620 /** PPGTT used for aliasing the PPGTT with the GTT */
621 struct i915_hw_ppgtt *aliasing_ppgtt;
622
623 struct shrinker inactive_shrinker;
624
625 /**
626 * List of objects currently involved in rendering.
627 *
628 * Includes buffers having the contents of their GPU caches
629 * flushed, not necessarily primitives. last_rendering_seqno
630 * represents when the rendering involved will be completed.
631 *
632 * A reference is held on the buffer while on this list.
633 */
634 struct list_head active_list;
635
636 /**
637 * List of objects which are not in the ringbuffer but which
638 * still have a write_domain which needs to be flushed before
639 * unbinding.
640 *
641 * last_rendering_seqno is 0 while an object is in this list.
642 *
643 * A reference is held on the buffer while on this list.
644 */
645 struct list_head flushing_list;
646
647 /**
648 * LRU list of objects which are not in the ringbuffer and
649 * are ready to unbind, but are still in the GTT.
650 *
651 * last_rendering_seqno is 0 while an object is in this list.
652 *
653 * A reference is not held on the buffer while on this list,
654 * as merely being GTT-bound shouldn't prevent its being
655 * freed, and we'll pull it off the list in the free path.
656 */
657 struct list_head inactive_list;
658
659 /**
660 * LRU list of objects which are not in the ringbuffer but
661 * are still pinned in the GTT.
662 */
663 struct list_head pinned_list;
664
665 /** LRU list of objects with fence regs on them. */
666 struct list_head fence_list;
667
668 /**
669 * List of objects currently pending being freed.
670 *
671 * These objects are no longer in use, but due to a signal
672 * we were prevented from freeing them at the appointed time.
673 */
674 struct list_head deferred_free_list;
675
676 /**
677 * We leave the user IRQ off as much as possible,
678 * but this means that requests will finish and never
679 * be retired once the system goes idle. Set a timer to
680 * fire periodically while the ring is running. When it
681 * fires, go retire requests.
682 */
683 struct delayed_work retire_work;
684
685 /**
686 * Are we in a non-interruptible section of code like
687 * modesetting?
688 */
689 bool interruptible;
690
691 /**
692 * Flag if the X Server, and thus DRM, is not currently in
693 * control of the device.
694 *
695 * This is set between LeaveVT and EnterVT. It needs to be
696 * replaced with a semaphore. It also needs to be
697 * transitioned away from for kernel modesetting.
698 */
699 int suspended;
700
701 /**
702 * Flag if the hardware appears to be wedged.
703 *
704 * This is set when attempts to idle the device timeout.
705 * It prevents command submission from occurring and makes
706 * every pending request fail
707 */
708 atomic_t wedged;
709
710 /** Bit 6 swizzling required for X tiling */
711 uint32_t bit_6_swizzle_x;
712 /** Bit 6 swizzling required for Y tiling */
713 uint32_t bit_6_swizzle_y;
714
715 /* storage for physical objects */
716 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
717
718 /* accounting, useful for userland debugging */
719 size_t gtt_total;
720 size_t mappable_gtt_total;
721 size_t object_memory;
722 u32 object_count;
723 } mm;
724 struct sdvo_device_mapping sdvo_mappings[2];
725 /* indicate whether the LVDS_BORDER should be enabled or not */
726 unsigned int lvds_border_bits;
727 /* Panel fitter placement and size for Ironlake+ */
728 u32 pch_pf_pos, pch_pf_size;
729
730 struct drm_crtc *plane_to_crtc_mapping[3];
731 struct drm_crtc *pipe_to_crtc_mapping[3];
732 wait_queue_head_t pending_flip_queue;
733 bool flip_pending_is_done;
734
735 /* Reclocking support */
736 bool render_reclock_avail;
737 bool lvds_downclock_avail;
738 /* indicates the reduced downclock for LVDS*/
739 int lvds_downclock;
740 struct work_struct idle_work;
741 struct timer_list idle_timer;
742 bool busy;
743 u16 orig_clock;
744 int child_dev_num;
745 struct child_device_config *child_dev;
746 struct drm_connector *int_lvds_connector;
747 struct drm_connector *int_edp_connector;
748
749 bool mchbar_need_disable;
750
751 struct work_struct rps_work;
752 spinlock_t rps_lock;
753 u32 pm_iir;
754
755 u8 cur_delay;
756 u8 min_delay;
757 u8 max_delay;
758 u8 fmax;
759 u8 fstart;
760
761 u64 last_count1;
762 unsigned long last_time1;
763 unsigned long chipset_power;
764 u64 last_count2;
765 struct timespec last_time2;
766 unsigned long gfx_power;
767 int c_m;
768 int r_t;
769 u8 corr;
770 spinlock_t *mchdev_lock;
771
772 enum no_fbc_reason no_fbc_reason;
773
774 struct drm_mm_node *compressed_fb;
775 struct drm_mm_node *compressed_llb;
776
777 unsigned long last_gpu_reset;
778
779 /* list of fbdev register on this device */
780 struct intel_fbdev *fbdev;
781
782 struct backlight_device *backlight;
783
784 struct drm_property *broadcast_rgb_property;
785 struct drm_property *force_audio_property;
786 } drm_i915_private_t;
787
788 enum hdmi_force_audio {
789 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
790 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
791 HDMI_AUDIO_AUTO, /* trust EDID */
792 HDMI_AUDIO_ON, /* force turn on HDMI audio */
793 };
794
795 enum i915_cache_level {
796 I915_CACHE_NONE,
797 I915_CACHE_LLC,
798 I915_CACHE_LLC_MLC, /* gen6+ */
799 };
800
801 struct drm_i915_gem_object {
802 struct drm_gem_object base;
803
804 /** Current space allocated to this object in the GTT, if any. */
805 struct drm_mm_node *gtt_space;
806 struct list_head gtt_list;
807
808 /** This object's place on the active/flushing/inactive lists */
809 struct list_head ring_list;
810 struct list_head mm_list;
811 /** This object's place on GPU write list */
812 struct list_head gpu_write_list;
813 /** This object's place in the batchbuffer or on the eviction list */
814 struct list_head exec_list;
815
816 /**
817 * This is set if the object is on the active or flushing lists
818 * (has pending rendering), and is not set if it's on inactive (ready
819 * to be unbound).
820 */
821 unsigned int active:1;
822
823 /**
824 * This is set if the object has been written to since last bound
825 * to the GTT
826 */
827 unsigned int dirty:1;
828
829 /**
830 * This is set if the object has been written to since the last
831 * GPU flush.
832 */
833 unsigned int pending_gpu_write:1;
834
835 /**
836 * Fence register bits (if any) for this object. Will be set
837 * as needed when mapped into the GTT.
838 * Protected by dev->struct_mutex.
839 */
840 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
841
842 /**
843 * Advice: are the backing pages purgeable?
844 */
845 unsigned int madv:2;
846
847 /**
848 * Current tiling mode for the object.
849 */
850 unsigned int tiling_mode:2;
851 unsigned int tiling_changed:1;
852
853 /** How many users have pinned this object in GTT space. The following
854 * users can each hold at most one reference: pwrite/pread, pin_ioctl
855 * (via user_pin_count), execbuffer (objects are not allowed multiple
856 * times for the same batchbuffer), and the framebuffer code. When
857 * switching/pageflipping, the framebuffer code has at most two buffers
858 * pinned per crtc.
859 *
860 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
861 * bits with absolutely no headroom. So use 4 bits. */
862 unsigned int pin_count:4;
863 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
864
865 /**
866 * Is the object at the current location in the gtt mappable and
867 * fenceable? Used to avoid costly recalculations.
868 */
869 unsigned int map_and_fenceable:1;
870
871 /**
872 * Whether the current gtt mapping needs to be mappable (and isn't just
873 * mappable by accident). Track pin and fault separate for a more
874 * accurate mappable working set.
875 */
876 unsigned int fault_mappable:1;
877 unsigned int pin_mappable:1;
878
879 /*
880 * Is the GPU currently using a fence to access this buffer,
881 */
882 unsigned int pending_fenced_gpu_access:1;
883 unsigned int fenced_gpu_access:1;
884
885 unsigned int cache_level:2;
886
887 unsigned int has_aliasing_ppgtt_mapping:1;
888
889 struct page **pages;
890
891 /**
892 * DMAR support
893 */
894 struct scatterlist *sg_list;
895 int num_sg;
896
897 /**
898 * Used for performing relocations during execbuffer insertion.
899 */
900 struct hlist_node exec_node;
901 unsigned long exec_handle;
902 struct drm_i915_gem_exec_object2 *exec_entry;
903
904 /**
905 * Current offset of the object in GTT space.
906 *
907 * This is the same as gtt_space->start
908 */
909 uint32_t gtt_offset;
910
911 /** Breadcrumb of last rendering to the buffer. */
912 uint32_t last_rendering_seqno;
913 struct intel_ring_buffer *ring;
914
915 /** Breadcrumb of last fenced GPU access to the buffer. */
916 uint32_t last_fenced_seqno;
917 struct intel_ring_buffer *last_fenced_ring;
918
919 /** Current tiling stride for the object, if it's tiled. */
920 uint32_t stride;
921
922 /** Record of address bit 17 of each page at last unbind. */
923 unsigned long *bit_17;
924
925
926 /**
927 * If present, while GEM_DOMAIN_CPU is in the read domain this array
928 * flags which individual pages are valid.
929 */
930 uint8_t *page_cpu_valid;
931
932 /** User space pin count and filp owning the pin */
933 uint32_t user_pin_count;
934 struct drm_file *pin_filp;
935
936 /** for phy allocated objects */
937 struct drm_i915_gem_phys_object *phys_obj;
938
939 /**
940 * Number of crtcs where this object is currently the fb, but
941 * will be page flipped away on the next vblank. When it
942 * reaches 0, dev_priv->pending_flip_queue will be woken up.
943 */
944 atomic_t pending_flip;
945 };
946
947 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
948
949 /**
950 * Request queue structure.
951 *
952 * The request queue allows us to note sequence numbers that have been emitted
953 * and may be associated with active buffers to be retired.
954 *
955 * By keeping this list, we can avoid having to do questionable
956 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
957 * an emission time with seqnos for tracking how far ahead of the GPU we are.
958 */
959 struct drm_i915_gem_request {
960 /** On Which ring this request was generated */
961 struct intel_ring_buffer *ring;
962
963 /** GEM sequence number associated with this request. */
964 uint32_t seqno;
965
966 /** Postion in the ringbuffer of the end of the request */
967 u32 tail;
968
969 /** Time at which this request was emitted, in jiffies. */
970 unsigned long emitted_jiffies;
971
972 /** global list entry for this request */
973 struct list_head list;
974
975 struct drm_i915_file_private *file_priv;
976 /** file_priv list entry for this request */
977 struct list_head client_list;
978 };
979
980 struct drm_i915_file_private {
981 struct {
982 struct spinlock lock;
983 struct list_head request_list;
984 } mm;
985 };
986
987 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
988
989 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
990 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
991 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
992 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
993 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
994 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
995 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
996 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
997 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
998 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
999 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1000 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1001 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1002 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1003 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1004 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1005 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1006 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1007 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1008 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1009
1010 /*
1011 * The genX designation typically refers to the render engine, so render
1012 * capability related checks should use IS_GEN, while display and other checks
1013 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1014 * chips, etc.).
1015 */
1016 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1017 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1018 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1019 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1020 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1021 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1022
1023 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1024 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1025 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1026 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1027
1028 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1029
1030 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1031 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1032
1033 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1034 * rows, which changed the alignment requirements and fence programming.
1035 */
1036 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1037 IS_I915GM(dev)))
1038 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1039 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1040 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1041 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1042 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1043 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1044 /* dsparb controlled by hw only */
1045 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1046
1047 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1048 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1049 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1050
1051 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1052 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1053
1054 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1055 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1056 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1057
1058 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1059
1060 #include "i915_trace.h"
1061
1062 /**
1063 * RC6 is a special power stage which allows the GPU to enter an very
1064 * low-voltage mode when idle, using down to 0V while at this stage. This
1065 * stage is entered automatically when the GPU is idle when RC6 support is
1066 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1067 *
1068 * There are different RC6 modes available in Intel GPU, which differentiate
1069 * among each other with the latency required to enter and leave RC6 and
1070 * voltage consumed by the GPU in different states.
1071 *
1072 * The combination of the following flags define which states GPU is allowed
1073 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1074 * RC6pp is deepest RC6. Their support by hardware varies according to the
1075 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1076 * which brings the most power savings; deeper states save more power, but
1077 * require higher latency to switch to and wake up.
1078 */
1079 #define INTEL_RC6_ENABLE (1<<0)
1080 #define INTEL_RC6p_ENABLE (1<<1)
1081 #define INTEL_RC6pp_ENABLE (1<<2)
1082
1083 extern struct drm_ioctl_desc i915_ioctls[];
1084 extern int i915_max_ioctl;
1085 extern unsigned int i915_fbpercrtc __always_unused;
1086 extern int i915_panel_ignore_lid __read_mostly;
1087 extern unsigned int i915_powersave __read_mostly;
1088 extern int i915_semaphores __read_mostly;
1089 extern unsigned int i915_lvds_downclock __read_mostly;
1090 extern int i915_panel_use_ssc __read_mostly;
1091 extern int i915_vbt_sdvo_panel_type __read_mostly;
1092 extern int i915_enable_rc6 __read_mostly;
1093 extern int i915_enable_fbc __read_mostly;
1094 extern bool i915_enable_hangcheck __read_mostly;
1095 extern int i915_enable_ppgtt __read_mostly;
1096
1097 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1098 extern int i915_resume(struct drm_device *dev);
1099 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1100 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1101
1102 /* i915_dma.c */
1103 extern void i915_kernel_lost_context(struct drm_device * dev);
1104 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1105 extern int i915_driver_unload(struct drm_device *);
1106 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1107 extern void i915_driver_lastclose(struct drm_device * dev);
1108 extern void i915_driver_preclose(struct drm_device *dev,
1109 struct drm_file *file_priv);
1110 extern void i915_driver_postclose(struct drm_device *dev,
1111 struct drm_file *file_priv);
1112 extern int i915_driver_device_is_agp(struct drm_device * dev);
1113 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1114 unsigned long arg);
1115 extern int i915_emit_box(struct drm_device *dev,
1116 struct drm_clip_rect *box,
1117 int DR1, int DR4);
1118 extern int i915_reset(struct drm_device *dev, u8 flags);
1119 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1120 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1121 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1122 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1123
1124
1125 /* i915_irq.c */
1126 void i915_hangcheck_elapsed(unsigned long data);
1127 void i915_handle_error(struct drm_device *dev, bool wedged);
1128 extern int i915_irq_emit(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130 extern int i915_irq_wait(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132
1133 extern void intel_irq_init(struct drm_device *dev);
1134
1135 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv);
1137 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1138 struct drm_file *file_priv);
1139 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1140 struct drm_file *file_priv);
1141
1142 void
1143 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1144
1145 void
1146 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1147
1148 void intel_enable_asle(struct drm_device *dev);
1149
1150 #ifdef CONFIG_DEBUG_FS
1151 extern void i915_destroy_error_state(struct drm_device *dev);
1152 #else
1153 #define i915_destroy_error_state(x)
1154 #endif
1155
1156
1157 /* i915_gem.c */
1158 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1159 struct drm_file *file_priv);
1160 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1161 struct drm_file *file_priv);
1162 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1163 struct drm_file *file_priv);
1164 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1165 struct drm_file *file_priv);
1166 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1167 struct drm_file *file_priv);
1168 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1169 struct drm_file *file_priv);
1170 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1171 struct drm_file *file_priv);
1172 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1173 struct drm_file *file_priv);
1174 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1175 struct drm_file *file_priv);
1176 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1177 struct drm_file *file_priv);
1178 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file_priv);
1180 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1181 struct drm_file *file_priv);
1182 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1183 struct drm_file *file_priv);
1184 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1185 struct drm_file *file_priv);
1186 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1187 struct drm_file *file_priv);
1188 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1189 struct drm_file *file_priv);
1190 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1191 struct drm_file *file_priv);
1192 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1193 struct drm_file *file_priv);
1194 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1195 struct drm_file *file_priv);
1196 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1197 struct drm_file *file_priv);
1198 void i915_gem_load(struct drm_device *dev);
1199 int i915_gem_init_object(struct drm_gem_object *obj);
1200 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1201 uint32_t invalidate_domains,
1202 uint32_t flush_domains);
1203 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1204 size_t size);
1205 void i915_gem_free_object(struct drm_gem_object *obj);
1206 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1207 uint32_t alignment,
1208 bool map_and_fenceable);
1209 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1210 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1211 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1212 void i915_gem_lastclose(struct drm_device *dev);
1213
1214 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1215 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1216 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1217 struct intel_ring_buffer *ring,
1218 u32 seqno);
1219
1220 int i915_gem_dumb_create(struct drm_file *file_priv,
1221 struct drm_device *dev,
1222 struct drm_mode_create_dumb *args);
1223 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1224 uint32_t handle, uint64_t *offset);
1225 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1226 uint32_t handle);
1227 /**
1228 * Returns true if seq1 is later than seq2.
1229 */
1230 static inline bool
i915_seqno_passed(uint32_t seq1,uint32_t seq2)1231 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1232 {
1233 return (int32_t)(seq1 - seq2) >= 0;
1234 }
1235
1236 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1237
1238 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1239 struct intel_ring_buffer *pipelined);
1240 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1241
1242 static inline void
i915_gem_object_pin_fence(struct drm_i915_gem_object * obj)1243 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1244 {
1245 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1246 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1247 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1248 }
1249 }
1250
1251 static inline void
i915_gem_object_unpin_fence(struct drm_i915_gem_object * obj)1252 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1253 {
1254 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1255 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1256 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1257 }
1258 }
1259
1260 void i915_gem_retire_requests(struct drm_device *dev);
1261 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1262
1263 void i915_gem_reset(struct drm_device *dev);
1264 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1265 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1266 uint32_t read_domains,
1267 uint32_t write_domain);
1268 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1269 int __must_check i915_gem_init_hw(struct drm_device *dev);
1270 void i915_gem_init_swizzling(struct drm_device *dev);
1271 void i915_gem_init_ppgtt(struct drm_device *dev);
1272 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1273 void i915_gem_do_init(struct drm_device *dev,
1274 unsigned long start,
1275 unsigned long mappable_end,
1276 unsigned long end);
1277 int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
1278 int __must_check i915_gem_idle(struct drm_device *dev);
1279 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1280 struct drm_file *file,
1281 struct drm_i915_gem_request *request);
1282 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1283 uint32_t seqno,
1284 bool do_retire);
1285 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1286 int __must_check
1287 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1288 bool write);
1289 int __must_check
1290 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1291 u32 alignment,
1292 struct intel_ring_buffer *pipelined);
1293 int i915_gem_attach_phys_object(struct drm_device *dev,
1294 struct drm_i915_gem_object *obj,
1295 int id,
1296 int align);
1297 void i915_gem_detach_phys_object(struct drm_device *dev,
1298 struct drm_i915_gem_object *obj);
1299 void i915_gem_free_all_phys_object(struct drm_device *dev);
1300 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1301
1302 uint32_t
1303 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1304 uint32_t size,
1305 int tiling_mode);
1306
1307 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1308 enum i915_cache_level cache_level);
1309
1310 /* i915_gem_gtt.c */
1311 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1312 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1313 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1314 struct drm_i915_gem_object *obj,
1315 enum i915_cache_level cache_level);
1316 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1317 struct drm_i915_gem_object *obj);
1318
1319 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1320 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1321 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1322 enum i915_cache_level cache_level);
1323 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1324
1325 /* i915_gem_evict.c */
1326 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1327 unsigned alignment, bool mappable);
1328 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1329 bool purgeable_only);
1330 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1331 bool purgeable_only);
1332
1333 /* i915_gem_tiling.c */
1334 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1335 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1336 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1337
1338 /* i915_gem_debug.c */
1339 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1340 const char *where, uint32_t mark);
1341 #if WATCH_LISTS
1342 int i915_verify_lists(struct drm_device *dev);
1343 #else
1344 #define i915_verify_lists(dev) 0
1345 #endif
1346 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1347 int handle);
1348 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1349 const char *where, uint32_t mark);
1350
1351 /* i915_debugfs.c */
1352 int i915_debugfs_init(struct drm_minor *minor);
1353 void i915_debugfs_cleanup(struct drm_minor *minor);
1354
1355 /* i915_suspend.c */
1356 extern int i915_save_state(struct drm_device *dev);
1357 extern int i915_restore_state(struct drm_device *dev);
1358
1359 /* i915_suspend.c */
1360 extern int i915_save_state(struct drm_device *dev);
1361 extern int i915_restore_state(struct drm_device *dev);
1362
1363 /* intel_i2c.c */
1364 extern int intel_setup_gmbus(struct drm_device *dev);
1365 extern void intel_teardown_gmbus(struct drm_device *dev);
1366 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1367 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)1368 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1369 {
1370 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1371 }
1372 extern void intel_i2c_reset(struct drm_device *dev);
1373
1374 /* intel_opregion.c */
1375 extern int intel_opregion_setup(struct drm_device *dev);
1376 #ifdef CONFIG_ACPI
1377 extern void intel_opregion_init(struct drm_device *dev);
1378 extern void intel_opregion_fini(struct drm_device *dev);
1379 extern void intel_opregion_asle_intr(struct drm_device *dev);
1380 extern void intel_opregion_gse_intr(struct drm_device *dev);
1381 extern void intel_opregion_enable_asle(struct drm_device *dev);
1382 #else
intel_opregion_init(struct drm_device * dev)1383 static inline void intel_opregion_init(struct drm_device *dev) { return; }
intel_opregion_fini(struct drm_device * dev)1384 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
intel_opregion_asle_intr(struct drm_device * dev)1385 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
intel_opregion_gse_intr(struct drm_device * dev)1386 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
intel_opregion_enable_asle(struct drm_device * dev)1387 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1388 #endif
1389
1390 /* intel_acpi.c */
1391 #ifdef CONFIG_ACPI
1392 extern void intel_register_dsm_handler(void);
1393 extern void intel_unregister_dsm_handler(void);
1394 #else
intel_register_dsm_handler(void)1395 static inline void intel_register_dsm_handler(void) { return; }
intel_unregister_dsm_handler(void)1396 static inline void intel_unregister_dsm_handler(void) { return; }
1397 #endif /* CONFIG_ACPI */
1398
1399 /* modesetting */
1400 extern void intel_modeset_init(struct drm_device *dev);
1401 extern void intel_modeset_gem_init(struct drm_device *dev);
1402 extern void intel_modeset_cleanup(struct drm_device *dev);
1403 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1404 extern bool intel_fbc_enabled(struct drm_device *dev);
1405 extern void intel_disable_fbc(struct drm_device *dev);
1406 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1407 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1408 extern void ironlake_enable_rc6(struct drm_device *dev);
1409 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1410 extern void intel_detect_pch(struct drm_device *dev);
1411 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1412
1413 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1414 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1415 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1416 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1417
1418 /* overlay */
1419 #ifdef CONFIG_DEBUG_FS
1420 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1421 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1422
1423 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1424 extern void intel_display_print_error_state(struct seq_file *m,
1425 struct drm_device *dev,
1426 struct intel_display_error_state *error);
1427 #endif
1428
1429 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1430
1431 #define BEGIN_LP_RING(n) \
1432 intel_ring_begin(LP_RING(dev_priv), (n))
1433
1434 #define OUT_RING(x) \
1435 intel_ring_emit(LP_RING(dev_priv), x)
1436
1437 #define ADVANCE_LP_RING() \
1438 intel_ring_advance(LP_RING(dev_priv))
1439
1440 /**
1441 * Lock test for when it's just for synchronization of ring access.
1442 *
1443 * In that case, we don't need to do it when GEM is initialized as nobody else
1444 * has access to the ring.
1445 */
1446 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1447 if (LP_RING(dev->dev_private)->obj == NULL) \
1448 LOCK_TEST_WITH_RETURN(dev, file); \
1449 } while (0)
1450
1451 /* On SNB platform, before reading ring registers forcewake bit
1452 * must be set to prevent GT core from power down and stale values being
1453 * returned.
1454 */
1455 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1456 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1457 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1458
1459 #define __i915_read(x, y) \
1460 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1461
1462 __i915_read(8, b)
1463 __i915_read(16, w)
1464 __i915_read(32, l)
1465 __i915_read(64, q)
1466 #undef __i915_read
1467
1468 #define __i915_write(x, y) \
1469 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1470
1471 __i915_write(8, b)
1472 __i915_write(16, w)
1473 __i915_write(32, l)
1474 __i915_write(64, q)
1475 #undef __i915_write
1476
1477 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1478 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1479
1480 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1481 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1482 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1483 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1484
1485 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1486 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1487 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1488 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1489
1490 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1491 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1492
1493 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1494 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1495
1496
1497 #endif
1498