1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/init.h> 8 #include <linux/stringify.h> 9 #include <asm/asm-compat.h> 10 #include <asm/processor.h> 11 #include <asm/ppc-opcode.h> 12 #include <asm/firmware.h> 13 14 #ifndef __ASSEMBLY__ 15 #error __FILE__ should only be used in assembler files 16 #else 17 18 #define SZL (BITS_PER_LONG/8) 19 20 /* 21 * Stuff for accurate CPU time accounting. 22 * These macros handle transitions between user and system state 23 * in exception entry and exit and accumulate time to the 24 * user_time and system_time fields in the paca. 25 */ 26 27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING 28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 29 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 30 #define ACCOUNT_STOLEN_TIME 31 #else 32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 33 beq 2f; /* if from kernel mode */ \ 34 MFTB(ra); /* get timebase */ \ 35 ld rb,PACA_STARTTIME_USER(r13); \ 36 std ra,PACA_STARTTIME(r13); \ 37 subf rb,rb,ra; /* subtract start value */ \ 38 ld ra,PACA_USER_TIME(r13); \ 39 add ra,ra,rb; /* add on to user time */ \ 40 std ra,PACA_USER_TIME(r13); \ 41 2: 42 43 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 44 MFTB(ra); /* get timebase */ \ 45 ld rb,PACA_STARTTIME(r13); \ 46 std ra,PACA_STARTTIME_USER(r13); \ 47 subf rb,rb,ra; /* subtract start value */ \ 48 ld ra,PACA_SYSTEM_TIME(r13); \ 49 add ra,ra,rb; /* add on to system time */ \ 50 std ra,PACA_SYSTEM_TIME(r13) 51 52 #ifdef CONFIG_PPC_SPLPAR 53 #define ACCOUNT_STOLEN_TIME \ 54 BEGIN_FW_FTR_SECTION; \ 55 beq 33f; \ 56 /* from user - see if there are any DTL entries to process */ \ 57 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 58 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 59 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \ 60 cmpd cr1,r11,r10; \ 61 beq+ cr1,33f; \ 62 bl .accumulate_stolen_time; \ 63 ld r12,_MSR(r1); \ 64 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 65 33: \ 66 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 67 68 #else /* CONFIG_PPC_SPLPAR */ 69 #define ACCOUNT_STOLEN_TIME 70 71 #endif /* CONFIG_PPC_SPLPAR */ 72 73 #endif /* CONFIG_VIRT_CPU_ACCOUNTING */ 74 75 /* 76 * Macros for storing registers into and loading registers from 77 * exception frames. 78 */ 79 #ifdef __powerpc64__ 80 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 81 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 82 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 83 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 84 #else 85 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 86 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 87 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 88 SAVE_10GPRS(22, base) 89 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 90 REST_10GPRS(22, base) 91 #endif 92 93 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 94 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 95 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 96 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 97 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 98 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 99 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 100 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 101 102 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 103 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 104 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 105 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 106 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 107 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 108 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 109 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 110 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 111 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 112 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 113 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 114 115 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b 116 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 117 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 118 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 119 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 120 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 121 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b 122 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 123 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 124 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 125 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 126 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 127 128 /* Save the lower 32 VSRs in the thread VSR region */ 129 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b) 130 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 131 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 132 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 133 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 134 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 135 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b) 136 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 137 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 138 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 139 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 140 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 141 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 142 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b) 143 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 144 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 145 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 146 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 147 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 148 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b) 149 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 150 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 151 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 152 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 153 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 154 155 /* 156 * b = base register for addressing, o = base offset from register of 1st EVR 157 * n = first EVR, s = scratch 158 */ 159 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 160 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 161 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 162 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 163 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 164 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 165 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 166 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 167 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 168 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 169 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 170 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 171 172 /* Macros to adjust thread priority for hardware multithreading */ 173 #define HMT_VERY_LOW or 31,31,31 # very low priority 174 #define HMT_LOW or 1,1,1 175 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 176 #define HMT_MEDIUM or 2,2,2 177 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 178 #define HMT_HIGH or 3,3,3 179 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 180 181 #ifdef __KERNEL__ 182 #ifdef CONFIG_PPC64 183 184 #define XGLUE(a,b) a##b 185 #define GLUE(a,b) XGLUE(a,b) 186 187 #define _GLOBAL(name) \ 188 .section ".text"; \ 189 .align 2 ; \ 190 .globl name; \ 191 .globl GLUE(.,name); \ 192 .section ".opd","aw"; \ 193 name: \ 194 .quad GLUE(.,name); \ 195 .quad .TOC.@tocbase; \ 196 .quad 0; \ 197 .previous; \ 198 .type GLUE(.,name),@function; \ 199 GLUE(.,name): 200 201 #define _INIT_GLOBAL(name) \ 202 __REF; \ 203 .align 2 ; \ 204 .globl name; \ 205 .globl GLUE(.,name); \ 206 .section ".opd","aw"; \ 207 name: \ 208 .quad GLUE(.,name); \ 209 .quad .TOC.@tocbase; \ 210 .quad 0; \ 211 .previous; \ 212 .type GLUE(.,name),@function; \ 213 GLUE(.,name): 214 215 #define _KPROBE(name) \ 216 .section ".kprobes.text","a"; \ 217 .align 2 ; \ 218 .globl name; \ 219 .globl GLUE(.,name); \ 220 .section ".opd","aw"; \ 221 name: \ 222 .quad GLUE(.,name); \ 223 .quad .TOC.@tocbase; \ 224 .quad 0; \ 225 .previous; \ 226 .type GLUE(.,name),@function; \ 227 GLUE(.,name): 228 229 #define _STATIC(name) \ 230 .section ".text"; \ 231 .align 2 ; \ 232 .section ".opd","aw"; \ 233 name: \ 234 .quad GLUE(.,name); \ 235 .quad .TOC.@tocbase; \ 236 .quad 0; \ 237 .previous; \ 238 .type GLUE(.,name),@function; \ 239 GLUE(.,name): 240 241 #define _INIT_STATIC(name) \ 242 __REF; \ 243 .align 2 ; \ 244 .section ".opd","aw"; \ 245 name: \ 246 .quad GLUE(.,name); \ 247 .quad .TOC.@tocbase; \ 248 .quad 0; \ 249 .previous; \ 250 .type GLUE(.,name),@function; \ 251 GLUE(.,name): 252 253 #else /* 32-bit */ 254 255 #define _ENTRY(n) \ 256 .globl n; \ 257 n: 258 259 #define _GLOBAL(n) \ 260 .text; \ 261 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 262 .globl n; \ 263 n: 264 265 #define _KPROBE(n) \ 266 .section ".kprobes.text","a"; \ 267 .globl n; \ 268 n: 269 270 #endif 271 272 /* 273 * LOAD_REG_IMMEDIATE(rn, expr) 274 * Loads the value of the constant expression 'expr' into register 'rn' 275 * using immediate instructions only. Use this when it's important not 276 * to reference other data (i.e. on ppc64 when the TOC pointer is not 277 * valid) and when 'expr' is a constant or absolute address. 278 * 279 * LOAD_REG_ADDR(rn, name) 280 * Loads the address of label 'name' into register 'rn'. Use this when 281 * you don't particularly need immediate instructions only, but you need 282 * the whole address in one register (e.g. it's a structure address and 283 * you want to access various offsets within it). On ppc32 this is 284 * identical to LOAD_REG_IMMEDIATE. 285 * 286 * LOAD_REG_ADDRBASE(rn, name) 287 * ADDROFF(name) 288 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 289 * register 'rn'. ADDROFF(name) returns the remainder of the address as 290 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 291 * in size, so is suitable for use directly as an offset in load and store 292 * instructions. Use this when loading/storing a single word or less as: 293 * LOAD_REG_ADDRBASE(rX, name) 294 * ld rY,ADDROFF(name)(rX) 295 */ 296 #ifdef __powerpc64__ 297 #define LOAD_REG_IMMEDIATE(reg,expr) \ 298 lis (reg),(expr)@highest; \ 299 ori (reg),(reg),(expr)@higher; \ 300 rldicr (reg),(reg),32,31; \ 301 oris (reg),(reg),(expr)@h; \ 302 ori (reg),(reg),(expr)@l; 303 304 #define LOAD_REG_ADDR(reg,name) \ 305 ld (reg),name@got(r2) 306 307 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 308 #define ADDROFF(name) 0 309 310 /* offsets for stack frame layout */ 311 #define LRSAVE 16 312 313 #else /* 32-bit */ 314 315 #define LOAD_REG_IMMEDIATE(reg,expr) \ 316 lis (reg),(expr)@ha; \ 317 addi (reg),(reg),(expr)@l; 318 319 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 320 321 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha 322 #define ADDROFF(name) name@l 323 324 /* offsets for stack frame layout */ 325 #define LRSAVE 4 326 327 #endif 328 329 /* various errata or part fixups */ 330 #ifdef CONFIG_PPC601_SYNC_FIX 331 #define SYNC \ 332 BEGIN_FTR_SECTION \ 333 sync; \ 334 isync; \ 335 END_FTR_SECTION_IFSET(CPU_FTR_601) 336 #define SYNC_601 \ 337 BEGIN_FTR_SECTION \ 338 sync; \ 339 END_FTR_SECTION_IFSET(CPU_FTR_601) 340 #define ISYNC_601 \ 341 BEGIN_FTR_SECTION \ 342 isync; \ 343 END_FTR_SECTION_IFSET(CPU_FTR_601) 344 #else 345 #define SYNC 346 #define SYNC_601 347 #define ISYNC_601 348 #endif 349 350 #ifdef CONFIG_PPC_CELL 351 #define MFTB(dest) \ 352 90: mftb dest; \ 353 BEGIN_FTR_SECTION_NESTED(96); \ 354 cmpwi dest,0; \ 355 beq- 90b; \ 356 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 357 #else 358 #define MFTB(dest) mftb dest 359 #endif 360 361 #ifndef CONFIG_SMP 362 #define TLBSYNC 363 #else /* CONFIG_SMP */ 364 /* tlbsync is not implemented on 601 */ 365 #define TLBSYNC \ 366 BEGIN_FTR_SECTION \ 367 tlbsync; \ 368 sync; \ 369 END_FTR_SECTION_IFCLR(CPU_FTR_601) 370 #endif 371 372 373 /* 374 * This instruction is not implemented on the PPC 603 or 601; however, on 375 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 376 * All of these instructions exist in the 8xx, they have magical powers, 377 * and they must be used. 378 */ 379 380 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 381 #define tlbia \ 382 li r4,1024; \ 383 mtctr r4; \ 384 lis r4,KERNELBASE@h; \ 385 0: tlbie r4; \ 386 addi r4,r4,0x1000; \ 387 bdnz 0b 388 #endif 389 390 391 #ifdef CONFIG_IBM440EP_ERR42 392 #define PPC440EP_ERR42 isync 393 #else 394 #define PPC440EP_ERR42 395 #endif 396 397 /* 398 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 399 * keep the address intact to be compatible with code shared with 400 * 32-bit classic. 401 * 402 * On the other hand, I find it useful to have them behave as expected 403 * by their name (ie always do the addition) on 64-bit BookE 404 */ 405 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 406 #define toreal(rd) 407 #define fromreal(rd) 408 409 /* 410 * We use addis to ensure compatibility with the "classic" ppc versions of 411 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 412 * converting the address in r0, and so this version has to do that too 413 * (i.e. set register rd to 0 when rs == 0). 414 */ 415 #define tophys(rd,rs) \ 416 addis rd,rs,0 417 418 #define tovirt(rd,rs) \ 419 addis rd,rs,0 420 421 #elif defined(CONFIG_PPC64) 422 #define toreal(rd) /* we can access c000... in real mode */ 423 #define fromreal(rd) 424 425 #define tophys(rd,rs) \ 426 clrldi rd,rs,2 427 428 #define tovirt(rd,rs) \ 429 rotldi rd,rs,16; \ 430 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 431 rotldi rd,rd,48 432 #else 433 /* 434 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 435 * physical base address of RAM at compile time. 436 */ 437 #define toreal(rd) tophys(rd,rd) 438 #define fromreal(rd) tovirt(rd,rd) 439 440 #define tophys(rd,rs) \ 441 0: addis rd,rs,-PAGE_OFFSET@h; \ 442 .section ".vtop_fixup","aw"; \ 443 .align 1; \ 444 .long 0b; \ 445 .previous 446 447 #define tovirt(rd,rs) \ 448 0: addis rd,rs,PAGE_OFFSET@h; \ 449 .section ".ptov_fixup","aw"; \ 450 .align 1; \ 451 .long 0b; \ 452 .previous 453 #endif 454 455 #ifdef CONFIG_PPC_BOOK3S_64 456 #define RFI rfid 457 #define MTMSRD(r) mtmsrd r 458 #else 459 #define FIX_SRR1(ra, rb) 460 #ifndef CONFIG_40x 461 #define RFI rfi 462 #else 463 #define RFI rfi; b . /* Prevent prefetch past rfi */ 464 #endif 465 #define MTMSRD(r) mtmsr r 466 #define CLR_TOP32(r) 467 #endif 468 469 #endif /* __KERNEL__ */ 470 471 /* The boring bits... */ 472 473 /* Condition Register Bit Fields */ 474 475 #define cr0 0 476 #define cr1 1 477 #define cr2 2 478 #define cr3 3 479 #define cr4 4 480 #define cr5 5 481 #define cr6 6 482 #define cr7 7 483 484 485 /* General Purpose Registers (GPRs) */ 486 487 #define r0 0 488 #define r1 1 489 #define r2 2 490 #define r3 3 491 #define r4 4 492 #define r5 5 493 #define r6 6 494 #define r7 7 495 #define r8 8 496 #define r9 9 497 #define r10 10 498 #define r11 11 499 #define r12 12 500 #define r13 13 501 #define r14 14 502 #define r15 15 503 #define r16 16 504 #define r17 17 505 #define r18 18 506 #define r19 19 507 #define r20 20 508 #define r21 21 509 #define r22 22 510 #define r23 23 511 #define r24 24 512 #define r25 25 513 #define r26 26 514 #define r27 27 515 #define r28 28 516 #define r29 29 517 #define r30 30 518 #define r31 31 519 520 521 /* Floating Point Registers (FPRs) */ 522 523 #define fr0 0 524 #define fr1 1 525 #define fr2 2 526 #define fr3 3 527 #define fr4 4 528 #define fr5 5 529 #define fr6 6 530 #define fr7 7 531 #define fr8 8 532 #define fr9 9 533 #define fr10 10 534 #define fr11 11 535 #define fr12 12 536 #define fr13 13 537 #define fr14 14 538 #define fr15 15 539 #define fr16 16 540 #define fr17 17 541 #define fr18 18 542 #define fr19 19 543 #define fr20 20 544 #define fr21 21 545 #define fr22 22 546 #define fr23 23 547 #define fr24 24 548 #define fr25 25 549 #define fr26 26 550 #define fr27 27 551 #define fr28 28 552 #define fr29 29 553 #define fr30 30 554 #define fr31 31 555 556 /* AltiVec Registers (VPRs) */ 557 558 #define vr0 0 559 #define vr1 1 560 #define vr2 2 561 #define vr3 3 562 #define vr4 4 563 #define vr5 5 564 #define vr6 6 565 #define vr7 7 566 #define vr8 8 567 #define vr9 9 568 #define vr10 10 569 #define vr11 11 570 #define vr12 12 571 #define vr13 13 572 #define vr14 14 573 #define vr15 15 574 #define vr16 16 575 #define vr17 17 576 #define vr18 18 577 #define vr19 19 578 #define vr20 20 579 #define vr21 21 580 #define vr22 22 581 #define vr23 23 582 #define vr24 24 583 #define vr25 25 584 #define vr26 26 585 #define vr27 27 586 #define vr28 28 587 #define vr29 29 588 #define vr30 30 589 #define vr31 31 590 591 /* VSX Registers (VSRs) */ 592 593 #define vsr0 0 594 #define vsr1 1 595 #define vsr2 2 596 #define vsr3 3 597 #define vsr4 4 598 #define vsr5 5 599 #define vsr6 6 600 #define vsr7 7 601 #define vsr8 8 602 #define vsr9 9 603 #define vsr10 10 604 #define vsr11 11 605 #define vsr12 12 606 #define vsr13 13 607 #define vsr14 14 608 #define vsr15 15 609 #define vsr16 16 610 #define vsr17 17 611 #define vsr18 18 612 #define vsr19 19 613 #define vsr20 20 614 #define vsr21 21 615 #define vsr22 22 616 #define vsr23 23 617 #define vsr24 24 618 #define vsr25 25 619 #define vsr26 26 620 #define vsr27 27 621 #define vsr28 28 622 #define vsr29 29 623 #define vsr30 30 624 #define vsr31 31 625 #define vsr32 32 626 #define vsr33 33 627 #define vsr34 34 628 #define vsr35 35 629 #define vsr36 36 630 #define vsr37 37 631 #define vsr38 38 632 #define vsr39 39 633 #define vsr40 40 634 #define vsr41 41 635 #define vsr42 42 636 #define vsr43 43 637 #define vsr44 44 638 #define vsr45 45 639 #define vsr46 46 640 #define vsr47 47 641 #define vsr48 48 642 #define vsr49 49 643 #define vsr50 50 644 #define vsr51 51 645 #define vsr52 52 646 #define vsr53 53 647 #define vsr54 54 648 #define vsr55 55 649 #define vsr56 56 650 #define vsr57 57 651 #define vsr58 58 652 #define vsr59 59 653 #define vsr60 60 654 #define vsr61 61 655 #define vsr62 62 656 #define vsr63 63 657 658 /* SPE Registers (EVPRs) */ 659 660 #define evr0 0 661 #define evr1 1 662 #define evr2 2 663 #define evr3 3 664 #define evr4 4 665 #define evr5 5 666 #define evr6 6 667 #define evr7 7 668 #define evr8 8 669 #define evr9 9 670 #define evr10 10 671 #define evr11 11 672 #define evr12 12 673 #define evr13 13 674 #define evr14 14 675 #define evr15 15 676 #define evr16 16 677 #define evr17 17 678 #define evr18 18 679 #define evr19 19 680 #define evr20 20 681 #define evr21 21 682 #define evr22 22 683 #define evr23 23 684 #define evr24 24 685 #define evr25 25 686 #define evr26 26 687 #define evr27 27 688 #define evr28 28 689 #define evr29 29 690 #define evr30 30 691 #define evr31 31 692 693 /* some stab codes */ 694 #define N_FUN 36 695 #define N_RSYM 64 696 #define N_SLINE 68 697 #define N_SO 100 698 699 #endif /* __ASSEMBLY__ */ 700 701 #endif /* _ASM_POWERPC_PPC_ASM_H */ 702