1 /*
2 * arch/arm/mach-vt8500/irq.c
3 *
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #include <linux/io.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24
25 #include <asm/irq.h>
26
27 #include "devices.h"
28
29 #define VT8500_IC_DCTR 0x40 /* Destination control
30 register, 64*u8 */
31 #define VT8500_INT_ENABLE (1 << 3)
32 #define VT8500_TRIGGER_HIGH (0 << 4)
33 #define VT8500_TRIGGER_RISING (1 << 4)
34 #define VT8500_TRIGGER_FALLING (2 << 4)
35 #define VT8500_EDGE ( VT8500_TRIGGER_RISING \
36 | VT8500_TRIGGER_FALLING)
37 #define VT8500_IC_STATUS 0x80 /* Interrupt status, 2*u32 */
38
39 static void __iomem *ic_regbase;
40 static void __iomem *sic_regbase;
41
vt8500_irq_mask(struct irq_data * d)42 static void vt8500_irq_mask(struct irq_data *d)
43 {
44 void __iomem *base = ic_regbase;
45 unsigned irq = d->irq;
46 u8 edge;
47
48 if (irq >= 64) {
49 base = sic_regbase;
50 irq -= 64;
51 }
52 edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
53 if (edge) {
54 void __iomem *stat_reg = base + VT8500_IC_STATUS
55 + (irq < 32 ? 0 : 4);
56 unsigned status = readl(stat_reg);
57
58 status |= (1 << (irq & 0x1f));
59 writel(status, stat_reg);
60 } else {
61 u8 dctr = readb(base + VT8500_IC_DCTR + irq);
62
63 dctr &= ~VT8500_INT_ENABLE;
64 writeb(dctr, base + VT8500_IC_DCTR + irq);
65 }
66 }
67
vt8500_irq_unmask(struct irq_data * d)68 static void vt8500_irq_unmask(struct irq_data *d)
69 {
70 void __iomem *base = ic_regbase;
71 unsigned irq = d->irq;
72 u8 dctr;
73
74 if (irq >= 64) {
75 base = sic_regbase;
76 irq -= 64;
77 }
78 dctr = readb(base + VT8500_IC_DCTR + irq);
79 dctr |= VT8500_INT_ENABLE;
80 writeb(dctr, base + VT8500_IC_DCTR + irq);
81 }
82
vt8500_irq_set_type(struct irq_data * d,unsigned int flow_type)83 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
84 {
85 void __iomem *base = ic_regbase;
86 unsigned irq = d->irq;
87 unsigned orig_irq = irq;
88 u8 dctr;
89
90 if (irq >= 64) {
91 base = sic_regbase;
92 irq -= 64;
93 }
94
95 dctr = readb(base + VT8500_IC_DCTR + irq);
96 dctr &= ~VT8500_EDGE;
97
98 switch (flow_type) {
99 case IRQF_TRIGGER_LOW:
100 return -EINVAL;
101 case IRQF_TRIGGER_HIGH:
102 dctr |= VT8500_TRIGGER_HIGH;
103 __irq_set_handler_locked(orig_irq, handle_level_irq);
104 break;
105 case IRQF_TRIGGER_FALLING:
106 dctr |= VT8500_TRIGGER_FALLING;
107 __irq_set_handler_locked(orig_irq, handle_edge_irq);
108 break;
109 case IRQF_TRIGGER_RISING:
110 dctr |= VT8500_TRIGGER_RISING;
111 __irq_set_handler_locked(orig_irq, handle_edge_irq);
112 break;
113 }
114 writeb(dctr, base + VT8500_IC_DCTR + irq);
115
116 return 0;
117 }
118
119 static struct irq_chip vt8500_irq_chip = {
120 .name = "vt8500",
121 .irq_ack = vt8500_irq_mask,
122 .irq_mask = vt8500_irq_mask,
123 .irq_unmask = vt8500_irq_unmask,
124 .irq_set_type = vt8500_irq_set_type,
125 };
126
vt8500_init_irq(void)127 void __init vt8500_init_irq(void)
128 {
129 unsigned int i;
130
131 ic_regbase = ioremap(wmt_ic_base, SZ_64K);
132
133 if (ic_regbase) {
134 /* Enable rotating priority for IRQ */
135 writel((1 << 6), ic_regbase + 0x20);
136 writel(0, ic_regbase + 0x24);
137
138 for (i = 0; i < wmt_nr_irqs; i++) {
139 /* Disable all interrupts and route them to IRQ */
140 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
141
142 irq_set_chip_and_handler(i, &vt8500_irq_chip,
143 handle_level_irq);
144 set_irq_flags(i, IRQF_VALID);
145 }
146 } else {
147 printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
148 }
149 }
150
wm8505_init_irq(void)151 void __init wm8505_init_irq(void)
152 {
153 unsigned int i;
154
155 ic_regbase = ioremap(wmt_ic_base, SZ_64K);
156 sic_regbase = ioremap(wmt_sic_base, SZ_64K);
157
158 if (ic_regbase && sic_regbase) {
159 /* Enable rotating priority for IRQ */
160 writel((1 << 6), ic_regbase + 0x20);
161 writel(0, ic_regbase + 0x24);
162 writel((1 << 6), sic_regbase + 0x20);
163 writel(0, sic_regbase + 0x24);
164
165 for (i = 0; i < wmt_nr_irqs; i++) {
166 /* Disable all interrupts and route them to IRQ */
167 if (i < 64)
168 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
169 else
170 writeb(0x00, sic_regbase + VT8500_IC_DCTR
171 + i - 64);
172
173 irq_set_chip_and_handler(i, &vt8500_irq_chip,
174 handle_level_irq);
175 set_irq_flags(i, IRQF_VALID);
176 }
177 } else {
178 printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
179 }
180 }
181