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1  #ifndef _ASM_X86_MSR_H
2  #define _ASM_X86_MSR_H
3  
4  #include <asm/msr-index.h>
5  
6  #ifndef __ASSEMBLY__
7  
8  #include <linux/types.h>
9  #include <linux/ioctl.h>
10  
11  #define X86_IOC_RDMSR_REGS	_IOWR('c', 0xA0, __u32[8])
12  #define X86_IOC_WRMSR_REGS	_IOWR('c', 0xA1, __u32[8])
13  
14  #ifdef __KERNEL__
15  
16  #include <asm/asm.h>
17  #include <asm/errno.h>
18  #include <asm/cpumask.h>
19  
20  struct msr {
21  	union {
22  		struct {
23  			u32 l;
24  			u32 h;
25  		};
26  		u64 q;
27  	};
28  };
29  
30  struct msr_info {
31  	u32 msr_no;
32  	struct msr reg;
33  	struct msr *msrs;
34  	int err;
35  };
36  
37  struct msr_regs_info {
38  	u32 *regs;
39  	int err;
40  };
41  
native_read_tscp(unsigned int * aux)42  static inline unsigned long long native_read_tscp(unsigned int *aux)
43  {
44  	unsigned long low, high;
45  	asm volatile(".byte 0x0f,0x01,0xf9"
46  		     : "=a" (low), "=d" (high), "=c" (*aux));
47  	return low | ((u64)high << 32);
48  }
49  
50  /*
51   * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
52   * constraint has different meanings. For i386, "A" means exactly
53   * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
54   * it means rax *or* rdx.
55   */
56  #ifdef CONFIG_X86_64
57  #define DECLARE_ARGS(val, low, high)	unsigned low, high
58  #define EAX_EDX_VAL(val, low, high)	((low) | ((u64)(high) << 32))
59  #define EAX_EDX_ARGS(val, low, high)	"a" (low), "d" (high)
60  #define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
61  #else
62  #define DECLARE_ARGS(val, low, high)	unsigned long long val
63  #define EAX_EDX_VAL(val, low, high)	(val)
64  #define EAX_EDX_ARGS(val, low, high)	"A" (val)
65  #define EAX_EDX_RET(val, low, high)	"=A" (val)
66  #endif
67  
native_read_msr(unsigned int msr)68  static inline unsigned long long native_read_msr(unsigned int msr)
69  {
70  	DECLARE_ARGS(val, low, high);
71  
72  	asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
73  	return EAX_EDX_VAL(val, low, high);
74  }
75  
native_read_msr_safe(unsigned int msr,int * err)76  static inline unsigned long long native_read_msr_safe(unsigned int msr,
77  						      int *err)
78  {
79  	DECLARE_ARGS(val, low, high);
80  
81  	asm volatile("2: rdmsr ; xor %[err],%[err]\n"
82  		     "1:\n\t"
83  		     ".section .fixup,\"ax\"\n\t"
84  		     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
85  		     ".previous\n\t"
86  		     _ASM_EXTABLE(2b, 3b)
87  		     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
88  		     : "c" (msr), [fault] "i" (-EIO));
89  	return EAX_EDX_VAL(val, low, high);
90  }
91  
native_write_msr(unsigned int msr,unsigned low,unsigned high)92  static inline void native_write_msr(unsigned int msr,
93  				    unsigned low, unsigned high)
94  {
95  	asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
96  }
97  
98  /* Can be uninlined because referenced by paravirt */
native_write_msr_safe(unsigned int msr,unsigned low,unsigned high)99  notrace static inline int native_write_msr_safe(unsigned int msr,
100  					unsigned low, unsigned high)
101  {
102  	int err;
103  	asm volatile("2: wrmsr ; xor %[err],%[err]\n"
104  		     "1:\n\t"
105  		     ".section .fixup,\"ax\"\n\t"
106  		     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
107  		     ".previous\n\t"
108  		     _ASM_EXTABLE(2b, 3b)
109  		     : [err] "=a" (err)
110  		     : "c" (msr), "0" (low), "d" (high),
111  		       [fault] "i" (-EIO)
112  		     : "memory");
113  	return err;
114  }
115  
116  extern unsigned long long native_read_tsc(void);
117  
118  extern int native_rdmsr_safe_regs(u32 regs[8]);
119  extern int native_wrmsr_safe_regs(u32 regs[8]);
120  
__native_read_tsc(void)121  static __always_inline unsigned long long __native_read_tsc(void)
122  {
123  	DECLARE_ARGS(val, low, high);
124  
125  	asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
126  
127  	return EAX_EDX_VAL(val, low, high);
128  }
129  
native_read_pmc(int counter)130  static inline unsigned long long native_read_pmc(int counter)
131  {
132  	DECLARE_ARGS(val, low, high);
133  
134  	asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
135  	return EAX_EDX_VAL(val, low, high);
136  }
137  
138  #ifdef CONFIG_PARAVIRT
139  #include <asm/paravirt.h>
140  #else
141  #include <linux/errno.h>
142  /*
143   * Access to machine-specific registers (available on 586 and better only)
144   * Note: the rd* operations modify the parameters directly (without using
145   * pointer indirection), this allows gcc to optimize better
146   */
147  
148  #define rdmsr(msr, val1, val2)					\
149  do {								\
150  	u64 __val = native_read_msr((msr));			\
151  	(void)((val1) = (u32)__val);				\
152  	(void)((val2) = (u32)(__val >> 32));			\
153  } while (0)
154  
wrmsr(unsigned msr,unsigned low,unsigned high)155  static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
156  {
157  	native_write_msr(msr, low, high);
158  }
159  
160  #define rdmsrl(msr, val)			\
161  	((val) = native_read_msr((msr)))
162  
163  #define wrmsrl(msr, val)						\
164  	native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
165  
166  /* wrmsr with exception handling */
wrmsr_safe(unsigned msr,unsigned low,unsigned high)167  static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
168  {
169  	return native_write_msr_safe(msr, low, high);
170  }
171  
172  /*
173   * rdmsr with exception handling.
174   *
175   * Please note that the exception handling works only after we've
176   * switched to the "smart" #GP handler in trap_init() which knows about
177   * exception tables - using this macro earlier than that causes machine
178   * hangs on boxes which do not implement the @msr in the first argument.
179   */
180  #define rdmsr_safe(msr, p1, p2)					\
181  ({								\
182  	int __err;						\
183  	u64 __val = native_read_msr_safe((msr), &__err);	\
184  	(*p1) = (u32)__val;					\
185  	(*p2) = (u32)(__val >> 32);				\
186  	__err;							\
187  })
188  
rdmsrl_safe(unsigned msr,unsigned long long * p)189  static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
190  {
191  	int err;
192  
193  	*p = native_read_msr_safe(msr, &err);
194  	return err;
195  }
196  
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)197  static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
198  {
199  	u32 gprs[8] = { 0 };
200  	int err;
201  
202  	gprs[1] = msr;
203  	gprs[7] = 0x9c5a203a;
204  
205  	err = native_rdmsr_safe_regs(gprs);
206  
207  	*p = gprs[0] | ((u64)gprs[2] << 32);
208  
209  	return err;
210  }
211  
wrmsrl_amd_safe(unsigned msr,unsigned long long val)212  static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
213  {
214  	u32 gprs[8] = { 0 };
215  
216  	gprs[0] = (u32)val;
217  	gprs[1] = msr;
218  	gprs[2] = val >> 32;
219  	gprs[7] = 0x9c5a203a;
220  
221  	return native_wrmsr_safe_regs(gprs);
222  }
223  
rdmsr_safe_regs(u32 regs[8])224  static inline int rdmsr_safe_regs(u32 regs[8])
225  {
226  	return native_rdmsr_safe_regs(regs);
227  }
228  
wrmsr_safe_regs(u32 regs[8])229  static inline int wrmsr_safe_regs(u32 regs[8])
230  {
231  	return native_wrmsr_safe_regs(regs);
232  }
233  
234  #define rdtscl(low)						\
235  	((low) = (u32)__native_read_tsc())
236  
237  #define rdtscll(val)						\
238  	((val) = __native_read_tsc())
239  
240  #define rdpmc(counter, low, high)			\
241  do {							\
242  	u64 _l = native_read_pmc((counter));		\
243  	(low)  = (u32)_l;				\
244  	(high) = (u32)(_l >> 32);			\
245  } while (0)
246  
247  #define rdtscp(low, high, aux)					\
248  do {                                                            \
249  	unsigned long long _val = native_read_tscp(&(aux));     \
250  	(low) = (u32)_val;                                      \
251  	(high) = (u32)(_val >> 32);                             \
252  } while (0)
253  
254  #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
255  
256  #endif	/* !CONFIG_PARAVIRT */
257  
258  
259  #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),		\
260  					     (u32)((val) >> 32))
261  
262  #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
263  
264  #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
265  
266  struct msr *msrs_alloc(void);
267  void msrs_free(struct msr *msrs);
268  
269  #ifdef CONFIG_SMP
270  int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
271  int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
272  void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
273  void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
274  int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
275  int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
276  int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
277  int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
278  #else  /*  CONFIG_SMP  */
rdmsr_on_cpu(unsigned int cpu,u32 msr_no,u32 * l,u32 * h)279  static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
280  {
281  	rdmsr(msr_no, *l, *h);
282  	return 0;
283  }
wrmsr_on_cpu(unsigned int cpu,u32 msr_no,u32 l,u32 h)284  static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
285  {
286  	wrmsr(msr_no, l, h);
287  	return 0;
288  }
rdmsr_on_cpus(const struct cpumask * m,u32 msr_no,struct msr * msrs)289  static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
290  				struct msr *msrs)
291  {
292         rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
293  }
wrmsr_on_cpus(const struct cpumask * m,u32 msr_no,struct msr * msrs)294  static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
295  				struct msr *msrs)
296  {
297         wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
298  }
rdmsr_safe_on_cpu(unsigned int cpu,u32 msr_no,u32 * l,u32 * h)299  static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
300  				    u32 *l, u32 *h)
301  {
302  	return rdmsr_safe(msr_no, l, h);
303  }
wrmsr_safe_on_cpu(unsigned int cpu,u32 msr_no,u32 l,u32 h)304  static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
305  {
306  	return wrmsr_safe(msr_no, l, h);
307  }
rdmsr_safe_regs_on_cpu(unsigned int cpu,u32 regs[8])308  static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
309  {
310  	return rdmsr_safe_regs(regs);
311  }
wrmsr_safe_regs_on_cpu(unsigned int cpu,u32 regs[8])312  static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
313  {
314  	return wrmsr_safe_regs(regs);
315  }
316  #endif  /* CONFIG_SMP */
317  #endif /* __KERNEL__ */
318  #endif /* __ASSEMBLY__ */
319  #endif /* _ASM_X86_MSR_H */
320