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1/*
2 * Kernel execution entry point code.
3 *
4 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 *	Initial PowerPC version.
6 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 *	Rewritten for PReP
8 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 *	Low-level exception handers, MMU support, and rewrite.
10 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 *	PowerPC 8xx modifications.
12 *    Copyright (c) 1998-1999 TiVo, Inc.
13 *	PowerPC 403GCX modifications.
14 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 *	PowerPC 403GCX/405GP modifications.
16 *    Copyright 2000 MontaVista Software Inc.
17 *	PPC405 modifications
18 *	PowerPC 403GCX/405GP modifications.
19 *	Author: MontaVista Software, Inc.
20 *		frank_rowand@mvista.com or source@mvista.com
21 *		debbie_chu@mvista.com
22 *    Copyright 2002-2004 MontaVista Software, Inc.
23 *	PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 *    Copyright 2004 Freescale Semiconductor, Inc
25 *	PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute  it and/or modify it
28 * under  the terms of  the GNU General  Public License as published by the
29 * Free Software Foundation;  either version 2 of the  License, or (at your
30 * option) any later version.
31 */
32
33#include <linux/init.h>
34#include <linux/threads.h>
35#include <asm/processor.h>
36#include <asm/page.h>
37#include <asm/mmu.h>
38#include <asm/pgtable.h>
39#include <asm/cputable.h>
40#include <asm/thread_info.h>
41#include <asm/ppc_asm.h>
42#include <asm/asm-offsets.h>
43#include <asm/cache.h>
44#include <asm/ptrace.h>
45#include "head_booke.h"
46
47/* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 *   r4 - Starting address of the init RAM disk
53 *   r5 - Ending address of the init RAM disk
54 *   r6 - Start of kernel command line string (e.g. "mem=128")
55 *   r7 - End of kernel command line string
56 *
57 */
58	__HEAD
59_ENTRY(_stext);
60_ENTRY(_start);
61	/*
62	 * Reserve a word at a fixed location to store the address
63	 * of abatron_pteptrs
64	 */
65	nop
66
67	/* Translate device tree address to physical, save in r30/r31 */
68	mfmsr	r16
69	mfspr	r17,SPRN_PID
70	rlwinm	r17,r17,16,0x3fff0000	/* turn PID into MAS6[SPID] */
71	rlwimi	r17,r16,28,0x00000001	/* turn MSR[DS] into MAS6[SAS] */
72	mtspr	SPRN_MAS6,r17
73
74	tlbsx	0,r3			/* must succeed */
75
76	mfspr	r16,SPRN_MAS1
77	mfspr	r20,SPRN_MAS3
78	rlwinm	r17,r16,25,0x1f		/* r17 = log2(page size) */
79	li	r18,1024
80	slw	r18,r18,r17		/* r18 = page size */
81	addi	r18,r18,-1
82	and	r19,r3,r18		/* r19 = page offset */
83	andc	r31,r20,r18		/* r31 = page base */
84	or	r31,r31,r19		/* r31 = devtree phys addr */
85	mfspr	r30,SPRN_MAS7
86
87	li	r25,0			/* phys kernel start (low) */
88	li	r24,0			/* CPU number */
89	li	r23,0			/* phys kernel start (high) */
90
91/* We try to not make any assumptions about how the boot loader
92 * setup or used the TLBs.  We invalidate all mappings from the
93 * boot loader and load a single entry in TLB1[0] to map the
94 * first 64M of kernel memory.  Any boot info passed from the
95 * bootloader needs to live in this first 64M.
96 *
97 * Requirement on bootloader:
98 *  - The page we're executing in needs to reside in TLB1 and
99 *    have IPROT=1.  If not an invalidate broadcast could
100 *    evict the entry we're currently executing in.
101 *
102 *  r3 = Index of TLB1 were executing in
103 *  r4 = Current MSR[IS]
104 *  r5 = Index of TLB1 temp mapping
105 *
106 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
107 * if needed
108 */
109
110_ENTRY(__early_start)
111
112#define ENTRY_MAPPING_BOOT_SETUP
113#include "fsl_booke_entry_mapping.S"
114#undef ENTRY_MAPPING_BOOT_SETUP
115
116	/* Establish the interrupt vector offsets */
117	SET_IVOR(0,  CriticalInput);
118	SET_IVOR(1,  MachineCheck);
119	SET_IVOR(2,  DataStorage);
120	SET_IVOR(3,  InstructionStorage);
121	SET_IVOR(4,  ExternalInput);
122	SET_IVOR(5,  Alignment);
123	SET_IVOR(6,  Program);
124	SET_IVOR(7,  FloatingPointUnavailable);
125	SET_IVOR(8,  SystemCall);
126	SET_IVOR(9,  AuxillaryProcessorUnavailable);
127	SET_IVOR(10, Decrementer);
128	SET_IVOR(11, FixedIntervalTimer);
129	SET_IVOR(12, WatchdogTimer);
130	SET_IVOR(13, DataTLBError);
131	SET_IVOR(14, InstructionTLBError);
132	SET_IVOR(15, DebugCrit);
133
134	/* Establish the interrupt vector base */
135	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
136	mtspr	SPRN_IVPR,r4
137
138	/* Setup the defaults for TLB entries */
139	li	r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
140#ifdef CONFIG_E200
141	oris	r2,r2,MAS4_TLBSELD(1)@h
142#endif
143	mtspr	SPRN_MAS4, r2
144
145#if 0
146	/* Enable DOZE */
147	mfspr	r2,SPRN_HID0
148	oris	r2,r2,HID0_DOZE@h
149	mtspr	SPRN_HID0, r2
150#endif
151
152#if !defined(CONFIG_BDI_SWITCH)
153	/*
154	 * The Abatron BDI JTAG debugger does not tolerate others
155	 * mucking with the debug registers.
156	 */
157	lis	r2,DBCR0_IDM@h
158	mtspr	SPRN_DBCR0,r2
159	isync
160	/* clear any residual debug events */
161	li	r2,-1
162	mtspr	SPRN_DBSR,r2
163#endif
164
165#ifdef CONFIG_SMP
166	/* Check to see if we're the second processor, and jump
167	 * to the secondary_start code if so
168	 */
169	lis	r24, boot_cpuid@h
170	ori	r24, r24, boot_cpuid@l
171	lwz	r24, 0(r24)
172	cmpwi	r24, -1
173	mfspr   r24,SPRN_PIR
174	bne	__secondary_start
175#endif
176
177	/*
178	 * This is where the main kernel code starts.
179	 */
180
181	/* ptr to current */
182	lis	r2,init_task@h
183	ori	r2,r2,init_task@l
184
185	/* ptr to current thread */
186	addi	r4,r2,THREAD	/* init task's THREAD */
187	mtspr	SPRN_SPRG_THREAD,r4
188
189	/* stack */
190	lis	r1,init_thread_union@h
191	ori	r1,r1,init_thread_union@l
192	li	r0,0
193	stwu	r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
194
195	rlwinm  r22,r1,0,0,31-THREAD_SHIFT      /* current thread_info */
196	stw	r24, TI_CPU(r22)
197
198	bl	early_init
199
200#ifdef CONFIG_DYNAMIC_MEMSTART
201	lis	r3,kernstart_addr@ha
202	la	r3,kernstart_addr@l(r3)
203#ifdef CONFIG_PHYS_64BIT
204	stw	r23,0(r3)
205	stw	r25,4(r3)
206#else
207	stw	r25,0(r3)
208#endif
209#endif
210
211/*
212 * Decide what sort of machine this is and initialize the MMU.
213 */
214	mr	r3,r30
215	mr	r4,r31
216	bl	machine_init
217	bl	MMU_init
218
219	/* Setup PTE pointers for the Abatron bdiGDB */
220	lis	r6, swapper_pg_dir@h
221	ori	r6, r6, swapper_pg_dir@l
222	lis	r5, abatron_pteptrs@h
223	ori	r5, r5, abatron_pteptrs@l
224	lis	r4, KERNELBASE@h
225	ori	r4, r4, KERNELBASE@l
226	stw	r5, 0(r4)	/* Save abatron_pteptrs at a fixed location */
227	stw	r6, 0(r5)
228
229	/* Let's move on */
230	lis	r4,start_kernel@h
231	ori	r4,r4,start_kernel@l
232	lis	r3,MSR_KERNEL@h
233	ori	r3,r3,MSR_KERNEL@l
234	mtspr	SPRN_SRR0,r4
235	mtspr	SPRN_SRR1,r3
236	rfi			/* change context and jump to start_kernel */
237
238/* Macros to hide the PTE size differences
239 *
240 * FIND_PTE -- walks the page tables given EA & pgdir pointer
241 *   r10 -- EA of fault
242 *   r11 -- PGDIR pointer
243 *   r12 -- free
244 *   label 2: is the bailout case
245 *
246 * if we find the pte (fall through):
247 *   r11 is low pte word
248 *   r12 is pointer to the pte
249 *   r10 is the pshift from the PGD, if we're a hugepage
250 */
251#ifdef CONFIG_PTE_64BIT
252#ifdef CONFIG_HUGETLB_PAGE
253#define FIND_PTE	\
254	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
255	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
256	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
257	blt	1000f;			/* Normal non-huge page */	\
258	beq	2f;			/* Bail if no table */		\
259	oris	r11, r11, PD_HUGE@h;	/* Put back address bit */	\
260	andi.	r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */	\
261	xor	r12, r10, r11;		/* drop size bits from pointer */ \
262	b	1001f;							\
2631000:	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
264	li	r10, 0;			/* clear r10 */			\
2651001:	lwz	r11, 4(r12);		/* Get pte entry */
266#else
267#define FIND_PTE	\
268	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
269	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
270	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
271	beq	2f;			/* Bail if no table */		\
272	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
273	lwz	r11, 4(r12);		/* Get pte entry */
274#endif /* HUGEPAGE */
275#else /* !PTE_64BIT */
276#define FIND_PTE	\
277	rlwimi	r11, r10, 12, 20, 29;	/* Create L1 (pgdir/pmd) address */	\
278	lwz	r11, 0(r11);		/* Get L1 entry */			\
279	rlwinm.	r12, r11, 0, 0, 19;	/* Extract L2 (pte) base address */	\
280	beq	2f;			/* Bail if no table */			\
281	rlwimi	r12, r10, 22, 20, 29;	/* Compute PTE address */		\
282	lwz	r11, 0(r12);		/* Get Linux PTE */
283#endif
284
285/*
286 * Interrupt vector entry code
287 *
288 * The Book E MMUs are always on so we don't need to handle
289 * interrupts in real mode as with previous PPC processors. In
290 * this case we handle interrupts in the kernel virtual address
291 * space.
292 *
293 * Interrupt vectors are dynamically placed relative to the
294 * interrupt prefix as determined by the address of interrupt_base.
295 * The interrupt vectors offsets are programmed using the labels
296 * for each interrupt vector entry.
297 *
298 * Interrupt vectors must be aligned on a 16 byte boundary.
299 * We align on a 32 byte cache line boundary for good measure.
300 */
301
302interrupt_base:
303	/* Critical Input Interrupt */
304	CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
305
306	/* Machine Check Interrupt */
307#ifdef CONFIG_E200
308	/* no RFMCI, MCSRRs on E200 */
309	CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
310#else
311	MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
312#endif
313
314	/* Data Storage Interrupt */
315	START_EXCEPTION(DataStorage)
316	NORMAL_EXCEPTION_PROLOG
317	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it, pass arg3 */
318	stw	r5,_ESR(r11)
319	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it, pass arg2 */
320	andis.	r10,r5,(ESR_ILK|ESR_DLK)@h
321	bne	1f
322	EXC_XFER_LITE(0x0300, handle_page_fault)
3231:
324	addi	r3,r1,STACK_FRAME_OVERHEAD
325	EXC_XFER_EE_LITE(0x0300, CacheLockingException)
326
327	/* Instruction Storage Interrupt */
328	INSTRUCTION_STORAGE_EXCEPTION
329
330	/* External Input Interrupt */
331	EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
332
333	/* Alignment Interrupt */
334	ALIGNMENT_EXCEPTION
335
336	/* Program Interrupt */
337	PROGRAM_EXCEPTION
338
339	/* Floating Point Unavailable Interrupt */
340#ifdef CONFIG_PPC_FPU
341	FP_UNAVAILABLE_EXCEPTION
342#else
343#ifdef CONFIG_E200
344	/* E200 treats 'normal' floating point instructions as FP Unavail exception */
345	EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
346#else
347	EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
348#endif
349#endif
350
351	/* System Call Interrupt */
352	START_EXCEPTION(SystemCall)
353	NORMAL_EXCEPTION_PROLOG
354	EXC_XFER_EE_LITE(0x0c00, DoSyscall)
355
356	/* Auxiliary Processor Unavailable Interrupt */
357	EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
358
359	/* Decrementer Interrupt */
360	DECREMENTER_EXCEPTION
361
362	/* Fixed Internal Timer Interrupt */
363	/* TODO: Add FIT support */
364	EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
365
366	/* Watchdog Timer Interrupt */
367#ifdef CONFIG_BOOKE_WDT
368	CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
369#else
370	CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
371#endif
372
373	/* Data TLB Error Interrupt */
374	START_EXCEPTION(DataTLBError)
375	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
376	mfspr	r10, SPRN_SPRG_THREAD
377	stw	r11, THREAD_NORMSAVE(0)(r10)
378	stw	r12, THREAD_NORMSAVE(1)(r10)
379	stw	r13, THREAD_NORMSAVE(2)(r10)
380	mfcr	r13
381	stw	r13, THREAD_NORMSAVE(3)(r10)
382	mfspr	r10, SPRN_DEAR		/* Get faulting address */
383
384	/* If we are faulting a kernel address, we have to use the
385	 * kernel page tables.
386	 */
387	lis	r11, PAGE_OFFSET@h
388	cmplw	5, r10, r11
389	blt	5, 3f
390	lis	r11, swapper_pg_dir@h
391	ori	r11, r11, swapper_pg_dir@l
392
393	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
394	rlwinm	r12,r12,0,16,1
395	mtspr	SPRN_MAS1,r12
396
397	b	4f
398
399	/* Get the PGD for the current thread */
4003:
401	mfspr	r11,SPRN_SPRG_THREAD
402	lwz	r11,PGDIR(r11)
403
4044:
405	/* Mask of required permission bits. Note that while we
406	 * do copy ESR:ST to _PAGE_RW position as trying to write
407	 * to an RO page is pretty common, we don't do it with
408	 * _PAGE_DIRTY. We could do it, but it's a fairly rare
409	 * event so I'd rather take the overhead when it happens
410	 * rather than adding an instruction here. We should measure
411	 * whether the whole thing is worth it in the first place
412	 * as we could avoid loading SPRN_ESR completely in the first
413	 * place...
414	 *
415	 * TODO: Is it worth doing that mfspr & rlwimi in the first
416	 *       place or can we save a couple of instructions here ?
417	 */
418	mfspr	r12,SPRN_ESR
419#ifdef CONFIG_PTE_64BIT
420	li	r13,_PAGE_PRESENT
421	oris	r13,r13,_PAGE_ACCESSED@h
422#else
423	li	r13,_PAGE_PRESENT|_PAGE_ACCESSED
424#endif
425	rlwimi	r13,r12,11,29,29
426
427	FIND_PTE
428	andc.	r13,r13,r11		/* Check permission */
429
430#ifdef CONFIG_PTE_64BIT
431#ifdef CONFIG_SMP
432	subf	r13,r11,r12		/* create false data dep */
433	lwzx	r13,r11,r13		/* Get upper pte bits */
434#else
435	lwz	r13,0(r12)		/* Get upper pte bits */
436#endif
437#endif
438
439	bne	2f			/* Bail if permission/valid mismach */
440
441	/* Jump to common tlb load */
442	b	finish_tlb_load
4432:
444	/* The bailout.  Restore registers to pre-exception conditions
445	 * and call the heavyweights to help us out.
446	 */
447	mfspr	r10, SPRN_SPRG_THREAD
448	lwz	r11, THREAD_NORMSAVE(3)(r10)
449	mtcr	r11
450	lwz	r13, THREAD_NORMSAVE(2)(r10)
451	lwz	r12, THREAD_NORMSAVE(1)(r10)
452	lwz	r11, THREAD_NORMSAVE(0)(r10)
453	mfspr	r10, SPRN_SPRG_RSCRATCH0
454	b	DataStorage
455
456	/* Instruction TLB Error Interrupt */
457	/*
458	 * Nearly the same as above, except we get our
459	 * information from different registers and bailout
460	 * to a different point.
461	 */
462	START_EXCEPTION(InstructionTLBError)
463	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
464	mfspr	r10, SPRN_SPRG_THREAD
465	stw	r11, THREAD_NORMSAVE(0)(r10)
466	stw	r12, THREAD_NORMSAVE(1)(r10)
467	stw	r13, THREAD_NORMSAVE(2)(r10)
468	mfcr	r13
469	stw	r13, THREAD_NORMSAVE(3)(r10)
470	mfspr	r10, SPRN_SRR0		/* Get faulting address */
471
472	/* If we are faulting a kernel address, we have to use the
473	 * kernel page tables.
474	 */
475	lis	r11, PAGE_OFFSET@h
476	cmplw	5, r10, r11
477	blt	5, 3f
478	lis	r11, swapper_pg_dir@h
479	ori	r11, r11, swapper_pg_dir@l
480
481	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
482	rlwinm	r12,r12,0,16,1
483	mtspr	SPRN_MAS1,r12
484
485	/* Make up the required permissions for kernel code */
486#ifdef CONFIG_PTE_64BIT
487	li	r13,_PAGE_PRESENT | _PAGE_BAP_SX
488	oris	r13,r13,_PAGE_ACCESSED@h
489#else
490	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
491#endif
492	b	4f
493
494	/* Get the PGD for the current thread */
4953:
496	mfspr	r11,SPRN_SPRG_THREAD
497	lwz	r11,PGDIR(r11)
498
499	/* Make up the required permissions for user code */
500#ifdef CONFIG_PTE_64BIT
501	li	r13,_PAGE_PRESENT | _PAGE_BAP_UX
502	oris	r13,r13,_PAGE_ACCESSED@h
503#else
504	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
505#endif
506
5074:
508	FIND_PTE
509	andc.	r13,r13,r11		/* Check permission */
510
511#ifdef CONFIG_PTE_64BIT
512#ifdef CONFIG_SMP
513	subf	r13,r11,r12		/* create false data dep */
514	lwzx	r13,r11,r13		/* Get upper pte bits */
515#else
516	lwz	r13,0(r12)		/* Get upper pte bits */
517#endif
518#endif
519
520	bne	2f			/* Bail if permission mismach */
521
522	/* Jump to common TLB load point */
523	b	finish_tlb_load
524
5252:
526	/* The bailout.  Restore registers to pre-exception conditions
527	 * and call the heavyweights to help us out.
528	 */
529	mfspr	r10, SPRN_SPRG_THREAD
530	lwz	r11, THREAD_NORMSAVE(3)(r10)
531	mtcr	r11
532	lwz	r13, THREAD_NORMSAVE(2)(r10)
533	lwz	r12, THREAD_NORMSAVE(1)(r10)
534	lwz	r11, THREAD_NORMSAVE(0)(r10)
535	mfspr	r10, SPRN_SPRG_RSCRATCH0
536	b	InstructionStorage
537
538#ifdef CONFIG_SPE
539	/* SPE Unavailable */
540	START_EXCEPTION(SPEUnavailable)
541	NORMAL_EXCEPTION_PROLOG
542	bne	load_up_spe
543	addi	r3,r1,STACK_FRAME_OVERHEAD
544	EXC_XFER_EE_LITE(0x2010, KernelSPE)
545#else
546	EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
547#endif /* CONFIG_SPE */
548
549	/* SPE Floating Point Data */
550#ifdef CONFIG_SPE
551	EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
552
553	/* SPE Floating Point Round */
554	EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
555#else
556	EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
557	EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
558#endif /* CONFIG_SPE */
559
560	/* Performance Monitor */
561	EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
562
563	EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
564
565	CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
566
567	/* Debug Interrupt */
568	DEBUG_DEBUG_EXCEPTION
569	DEBUG_CRIT_EXCEPTION
570
571/*
572 * Local functions
573 */
574
575/*
576 * Both the instruction and data TLB miss get to this
577 * point to load the TLB.
578 *	r10 - tsize encoding (if HUGETLB_PAGE) or available to use
579 *	r11 - TLB (info from Linux PTE)
580 *	r12 - available to use
581 *	r13 - upper bits of PTE (if PTE_64BIT) or available to use
582 *	CR5 - results of addr >= PAGE_OFFSET
583 *	MAS0, MAS1 - loaded with proper value when we get here
584 *	MAS2, MAS3 - will need additional info from Linux PTE
585 *	Upon exit, we reload everything and RFI.
586 */
587finish_tlb_load:
588#ifdef CONFIG_HUGETLB_PAGE
589	cmpwi	6, r10, 0			/* check for huge page */
590	beq	6, finish_tlb_load_cont    	/* !huge */
591
592	/* Alas, we need more scratch registers for hugepages */
593	mfspr	r12, SPRN_SPRG_THREAD
594	stw	r14, THREAD_NORMSAVE(4)(r12)
595	stw	r15, THREAD_NORMSAVE(5)(r12)
596	stw	r16, THREAD_NORMSAVE(6)(r12)
597	stw	r17, THREAD_NORMSAVE(7)(r12)
598
599	/* Get the next_tlbcam_idx percpu var */
600#ifdef CONFIG_SMP
601	lwz	r12, THREAD_INFO-THREAD(r12)
602	lwz	r15, TI_CPU(r12)
603	lis     r14, __per_cpu_offset@h
604	ori     r14, r14, __per_cpu_offset@l
605	rlwinm  r15, r15, 2, 0, 29
606	lwzx    r16, r14, r15
607#else
608	li	r16, 0
609#endif
610	lis     r17, next_tlbcam_idx@h
611	ori	r17, r17, next_tlbcam_idx@l
612	add	r17, r17, r16			/* r17 = *next_tlbcam_idx */
613	lwz     r15, 0(r17)			/* r15 = next_tlbcam_idx */
614
615	lis	r14, MAS0_TLBSEL(1)@h		/* select TLB1 (TLBCAM) */
616	rlwimi	r14, r15, 16, 4, 15		/* next_tlbcam_idx entry */
617	mtspr	SPRN_MAS0, r14
618
619	/* Extract TLB1CFG(NENTRY) */
620	mfspr	r16, SPRN_TLB1CFG
621	andi.	r16, r16, 0xfff
622
623	/* Update next_tlbcam_idx, wrapping when necessary */
624	addi	r15, r15, 1
625	cmpw	r15, r16
626	blt 	100f
627	lis	r14, tlbcam_index@h
628	ori	r14, r14, tlbcam_index@l
629	lwz	r15, 0(r14)
630100:	stw	r15, 0(r17)
631
632	/*
633	 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
634	 * tlb_enc = (pshift - 10).
635	 */
636	subi	r15, r10, 10
637	mfspr	r16, SPRN_MAS1
638	rlwimi	r16, r15, 7, 20, 24
639	mtspr	SPRN_MAS1, r16
640
641	/* copy the pshift for use later */
642	mr	r14, r10
643
644	/* fall through */
645
646#endif /* CONFIG_HUGETLB_PAGE */
647
648	/*
649	 * We set execute, because we don't have the granularity to
650	 * properly set this at the page level (Linux problem).
651	 * Many of these bits are software only.  Bits we don't set
652	 * here we (properly should) assume have the appropriate value.
653	 */
654finish_tlb_load_cont:
655#ifdef CONFIG_PTE_64BIT
656	rlwinm	r12, r11, 32-2, 26, 31	/* Move in perm bits */
657	andi.	r10, r11, _PAGE_DIRTY
658	bne	1f
659	li	r10, MAS3_SW | MAS3_UW
660	andc	r12, r12, r10
6611:	rlwimi	r12, r13, 20, 0, 11	/* grab RPN[32:43] */
662	rlwimi	r12, r11, 20, 12, 19	/* grab RPN[44:51] */
6632:	mtspr	SPRN_MAS3, r12
664BEGIN_MMU_FTR_SECTION
665	srwi	r10, r13, 12		/* grab RPN[12:31] */
666	mtspr	SPRN_MAS7, r10
667END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
668#else
669	li	r10, (_PAGE_EXEC | _PAGE_PRESENT)
670	mr	r13, r11
671	rlwimi	r10, r11, 31, 29, 29	/* extract _PAGE_DIRTY into SW */
672	and	r12, r11, r10
673	andi.	r10, r11, _PAGE_USER	/* Test for _PAGE_USER */
674	slwi	r10, r12, 1
675	or	r10, r10, r12
676	iseleq	r12, r12, r10
677	rlwimi	r13, r12, 0, 20, 31	/* Get RPN from PTE, merge w/ perms */
678	mtspr	SPRN_MAS3, r13
679#endif
680
681	mfspr	r12, SPRN_MAS2
682#ifdef CONFIG_PTE_64BIT
683	rlwimi	r12, r11, 32-19, 27, 31	/* extract WIMGE from pte */
684#else
685	rlwimi	r12, r11, 26, 27, 31	/* extract WIMGE from pte */
686#endif
687#ifdef CONFIG_HUGETLB_PAGE
688	beq	6, 3f			/* don't mask if page isn't huge */
689	li	r13, 1
690	slw	r13, r13, r14
691	subi	r13, r13, 1
692	rlwinm	r13, r13, 0, 0, 19	/* bottom bits used for WIMGE/etc */
693	andc	r12, r12, r13		/* mask off ea bits within the page */
694#endif
6953:	mtspr	SPRN_MAS2, r12
696
697#ifdef CONFIG_E200
698	/* Round robin TLB1 entries assignment */
699	mfspr	r12, SPRN_MAS0
700
701	/* Extract TLB1CFG(NENTRY) */
702	mfspr	r11, SPRN_TLB1CFG
703	andi.	r11, r11, 0xfff
704
705	/* Extract MAS0(NV) */
706	andi.	r13, r12, 0xfff
707	addi	r13, r13, 1
708	cmpw	0, r13, r11
709	addi	r12, r12, 1
710
711	/* check if we need to wrap */
712	blt	7f
713
714	/* wrap back to first free tlbcam entry */
715	lis	r13, tlbcam_index@ha
716	lwz	r13, tlbcam_index@l(r13)
717	rlwimi	r12, r13, 0, 20, 31
7187:
719	mtspr	SPRN_MAS0,r12
720#endif /* CONFIG_E200 */
721
722tlb_write_entry:
723	tlbwe
724
725	/* Done...restore registers and get out of here.  */
726	mfspr	r10, SPRN_SPRG_THREAD
727#ifdef CONFIG_HUGETLB_PAGE
728	beq	6, 8f /* skip restore for 4k page faults */
729	lwz	r14, THREAD_NORMSAVE(4)(r10)
730	lwz	r15, THREAD_NORMSAVE(5)(r10)
731	lwz	r16, THREAD_NORMSAVE(6)(r10)
732	lwz	r17, THREAD_NORMSAVE(7)(r10)
733#endif
7348:	lwz	r11, THREAD_NORMSAVE(3)(r10)
735	mtcr	r11
736	lwz	r13, THREAD_NORMSAVE(2)(r10)
737	lwz	r12, THREAD_NORMSAVE(1)(r10)
738	lwz	r11, THREAD_NORMSAVE(0)(r10)
739	mfspr	r10, SPRN_SPRG_RSCRATCH0
740	rfi					/* Force context change */
741
742#ifdef CONFIG_SPE
743/* Note that the SPE support is closely modeled after the AltiVec
744 * support.  Changes to one are likely to be applicable to the
745 * other!  */
746load_up_spe:
747/*
748 * Disable SPE for the task which had SPE previously,
749 * and save its SPE registers in its thread_struct.
750 * Enables SPE for use in the kernel on return.
751 * On SMP we know the SPE units are free, since we give it up every
752 * switch.  -- Kumar
753 */
754	mfmsr	r5
755	oris	r5,r5,MSR_SPE@h
756	mtmsr	r5			/* enable use of SPE now */
757	isync
758/*
759 * For SMP, we don't do lazy SPE switching because it just gets too
760 * horrendously complex, especially when a task switches from one CPU
761 * to another.  Instead we call giveup_spe in switch_to.
762 */
763#ifndef CONFIG_SMP
764	lis	r3,last_task_used_spe@ha
765	lwz	r4,last_task_used_spe@l(r3)
766	cmpi	0,r4,0
767	beq	1f
768	addi	r4,r4,THREAD	/* want THREAD of last_task_used_spe */
769	SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
770	evxor	evr10, evr10, evr10	/* clear out evr10 */
771	evmwumiaa evr10, evr10, evr10	/* evr10 <- ACC = 0 * 0 + ACC */
772	li	r5,THREAD_ACC
773	evstddx	evr10, r4, r5		/* save off accumulator */
774	lwz	r5,PT_REGS(r4)
775	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
776	lis	r10,MSR_SPE@h
777	andc	r4,r4,r10	/* disable SPE for previous task */
778	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7791:
780#endif /* !CONFIG_SMP */
781	/* enable use of SPE after return */
782	oris	r9,r9,MSR_SPE@h
783	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
784	li	r4,1
785	li	r10,THREAD_ACC
786	stw	r4,THREAD_USED_SPE(r5)
787	evlddx	evr4,r10,r5
788	evmra	evr4,evr4
789	REST_32EVRS(0,r10,r5,THREAD_EVR0)
790#ifndef CONFIG_SMP
791	subi	r4,r5,THREAD
792	stw	r4,last_task_used_spe@l(r3)
793#endif /* !CONFIG_SMP */
794	/* restore registers and return */
7952:	REST_4GPRS(3, r11)
796	lwz	r10,_CCR(r11)
797	REST_GPR(1, r11)
798	mtcr	r10
799	lwz	r10,_LINK(r11)
800	mtlr	r10
801	REST_GPR(10, r11)
802	mtspr	SPRN_SRR1,r9
803	mtspr	SPRN_SRR0,r12
804	REST_GPR(9, r11)
805	REST_GPR(12, r11)
806	lwz	r11,GPR11(r11)
807	rfi
808
809/*
810 * SPE unavailable trap from kernel - print a message, but let
811 * the task use SPE in the kernel until it returns to user mode.
812 */
813KernelSPE:
814	lwz	r3,_MSR(r1)
815	oris	r3,r3,MSR_SPE@h
816	stw	r3,_MSR(r1)	/* enable use of SPE after return */
817#ifdef CONFIG_PRINTK
818	lis	r3,87f@h
819	ori	r3,r3,87f@l
820	mr	r4,r2		/* current */
821	lwz	r5,_NIP(r1)
822	bl	printk
823#endif
824	b	ret_from_except
825#ifdef CONFIG_PRINTK
82687:	.string	"SPE used in kernel  (task=%p, pc=%x)  \n"
827#endif
828	.align	4,0
829
830#endif /* CONFIG_SPE */
831
832/*
833 * Global functions
834 */
835
836/* Adjust or setup IVORs for e200 */
837_GLOBAL(__setup_e200_ivors)
838	li	r3,DebugDebug@l
839	mtspr	SPRN_IVOR15,r3
840	li	r3,SPEUnavailable@l
841	mtspr	SPRN_IVOR32,r3
842	li	r3,SPEFloatingPointData@l
843	mtspr	SPRN_IVOR33,r3
844	li	r3,SPEFloatingPointRound@l
845	mtspr	SPRN_IVOR34,r3
846	sync
847	blr
848
849/* Adjust or setup IVORs for e500v1/v2 */
850_GLOBAL(__setup_e500_ivors)
851	li	r3,DebugCrit@l
852	mtspr	SPRN_IVOR15,r3
853	li	r3,SPEUnavailable@l
854	mtspr	SPRN_IVOR32,r3
855	li	r3,SPEFloatingPointData@l
856	mtspr	SPRN_IVOR33,r3
857	li	r3,SPEFloatingPointRound@l
858	mtspr	SPRN_IVOR34,r3
859	li	r3,PerformanceMonitor@l
860	mtspr	SPRN_IVOR35,r3
861	sync
862	blr
863
864/* Adjust or setup IVORs for e500mc */
865_GLOBAL(__setup_e500mc_ivors)
866	li	r3,DebugDebug@l
867	mtspr	SPRN_IVOR15,r3
868	li	r3,PerformanceMonitor@l
869	mtspr	SPRN_IVOR35,r3
870	li	r3,Doorbell@l
871	mtspr	SPRN_IVOR36,r3
872	li	r3,CriticalDoorbell@l
873	mtspr	SPRN_IVOR37,r3
874	sync
875	blr
876
877/*
878 * extern void giveup_altivec(struct task_struct *prev)
879 *
880 * The e500 core does not have an AltiVec unit.
881 */
882_GLOBAL(giveup_altivec)
883	blr
884
885#ifdef CONFIG_SPE
886/*
887 * extern void giveup_spe(struct task_struct *prev)
888 *
889 */
890_GLOBAL(giveup_spe)
891	mfmsr	r5
892	oris	r5,r5,MSR_SPE@h
893	mtmsr	r5			/* enable use of SPE now */
894	isync
895	cmpi	0,r3,0
896	beqlr-				/* if no previous owner, done */
897	addi	r3,r3,THREAD		/* want THREAD of task */
898	lwz	r5,PT_REGS(r3)
899	cmpi	0,r5,0
900	SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
901	evxor	evr6, evr6, evr6	/* clear out evr6 */
902	evmwumiaa evr6, evr6, evr6	/* evr6 <- ACC = 0 * 0 + ACC */
903	li	r4,THREAD_ACC
904	evstddx	evr6, r4, r3		/* save off accumulator */
905	beq	1f
906	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
907	lis	r3,MSR_SPE@h
908	andc	r4,r4,r3		/* disable SPE for previous task */
909	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
9101:
911#ifndef CONFIG_SMP
912	li	r5,0
913	lis	r4,last_task_used_spe@ha
914	stw	r5,last_task_used_spe@l(r4)
915#endif /* !CONFIG_SMP */
916	blr
917#endif /* CONFIG_SPE */
918
919/*
920 * extern void giveup_fpu(struct task_struct *prev)
921 *
922 * Not all FSL Book-E cores have an FPU
923 */
924#ifndef CONFIG_PPC_FPU
925_GLOBAL(giveup_fpu)
926	blr
927#endif
928
929/*
930 * extern void abort(void)
931 *
932 * At present, this routine just applies a system reset.
933 */
934_GLOBAL(abort)
935	li	r13,0
936	mtspr	SPRN_DBCR0,r13		/* disable all debug events */
937	isync
938	mfmsr	r13
939	ori	r13,r13,MSR_DE@l	/* Enable Debug Events */
940	mtmsr	r13
941	isync
942	mfspr	r13,SPRN_DBCR0
943	lis	r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
944	mtspr	SPRN_DBCR0,r13
945	isync
946
947_GLOBAL(set_context)
948
949#ifdef CONFIG_BDI_SWITCH
950	/* Context switch the PTE pointer for the Abatron BDI2000.
951	 * The PGDIR is the second parameter.
952	 */
953	lis	r5, abatron_pteptrs@h
954	ori	r5, r5, abatron_pteptrs@l
955	stw	r4, 0x4(r5)
956#endif
957	mtspr	SPRN_PID,r3
958	isync			/* Force context change */
959	blr
960
961_GLOBAL(flush_dcache_L1)
962	mfspr	r3,SPRN_L1CFG0
963
964	rlwinm	r5,r3,9,3	/* Extract cache block size */
965	twlgti	r5,1		/* Only 32 and 64 byte cache blocks
966				 * are currently defined.
967				 */
968	li	r4,32
969	subfic	r6,r5,2		/* r6 = log2(1KiB / cache block size) -
970				 *      log2(number of ways)
971				 */
972	slw	r5,r4,r5	/* r5 = cache block size */
973
974	rlwinm	r7,r3,0,0xff	/* Extract number of KiB in the cache */
975	mulli	r7,r7,13	/* An 8-way cache will require 13
976				 * loads per set.
977				 */
978	slw	r7,r7,r6
979
980	/* save off HID0 and set DCFA */
981	mfspr	r8,SPRN_HID0
982	ori	r9,r8,HID0_DCFA@l
983	mtspr	SPRN_HID0,r9
984	isync
985
986	lis	r4,KERNELBASE@h
987	mtctr	r7
988
9891:	lwz	r3,0(r4)	/* Load... */
990	add	r4,r4,r5
991	bdnz	1b
992
993	msync
994	lis	r4,KERNELBASE@h
995	mtctr	r7
996
9971:	dcbf	0,r4		/* ...and flush. */
998	add	r4,r4,r5
999	bdnz	1b
1000
1001	/* restore HID0 */
1002	mtspr	SPRN_HID0,r8
1003	isync
1004
1005	blr
1006
1007#ifdef CONFIG_SMP
1008/* When we get here, r24 needs to hold the CPU # */
1009	.globl __secondary_start
1010__secondary_start:
1011	lis	r3,__secondary_hold_acknowledge@h
1012	ori	r3,r3,__secondary_hold_acknowledge@l
1013	stw	r24,0(r3)
1014
1015	li	r3,0
1016	mr	r4,r24		/* Why? */
1017	bl	call_setup_cpu
1018
1019	lis	r3,tlbcam_index@ha
1020	lwz	r3,tlbcam_index@l(r3)
1021	mtctr	r3
1022	li	r26,0		/* r26 safe? */
1023
1024	/* Load each CAM entry */
10251:	mr	r3,r26
1026	bl	loadcam_entry
1027	addi	r26,r26,1
1028	bdnz	1b
1029
1030	/* get current_thread_info and current */
1031	lis	r1,secondary_ti@ha
1032	lwz	r1,secondary_ti@l(r1)
1033	lwz	r2,TI_TASK(r1)
1034
1035	/* stack */
1036	addi	r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1037	li	r0,0
1038	stw	r0,0(r1)
1039
1040	/* ptr to current thread */
1041	addi	r4,r2,THREAD	/* address of our thread_struct */
1042	mtspr	SPRN_SPRG_THREAD,r4
1043
1044	/* Setup the defaults for TLB entries */
1045	li	r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1046	mtspr	SPRN_MAS4,r4
1047
1048	/* Jump to start_secondary */
1049	lis	r4,MSR_KERNEL@h
1050	ori	r4,r4,MSR_KERNEL@l
1051	lis	r3,start_secondary@h
1052	ori	r3,r3,start_secondary@l
1053	mtspr	SPRN_SRR0,r3
1054	mtspr	SPRN_SRR1,r4
1055	sync
1056	rfi
1057	sync
1058
1059	.globl __secondary_hold_acknowledge
1060__secondary_hold_acknowledge:
1061	.long	-1
1062#endif
1063
1064/*
1065 * We put a few things here that have to be page-aligned. This stuff
1066 * goes at the beginning of the data segment, which is page-aligned.
1067 */
1068	.data
1069	.align	12
1070	.globl	sdata
1071sdata:
1072	.globl	empty_zero_page
1073empty_zero_page:
1074	.space	4096
1075	.globl	swapper_pg_dir
1076swapper_pg_dir:
1077	.space	PGD_TABLE_SIZE
1078
1079/*
1080 * Room for two PTE pointers, usually the kernel and current user pointers
1081 * to their respective root page table.
1082 */
1083abatron_pteptrs:
1084	.space	8
1085