1 /* 2 * pcicfg.h: PCI configuration constants and structures. 3 * 4 * Copyright (C) 1999-2013, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: pcicfg.h 346935 2012-07-25 00:24:55Z $ 25 */ 26 27 #ifndef _h_pcicfg_ 28 #define _h_pcicfg_ 29 30 /* A structure for the config registers is nice, but in most 31 * systems the config space is not memory mapped, so we need 32 * field offsetts. :-( 33 */ 34 #define PCI_CFG_VID 0 35 #define PCI_CFG_DID 2 36 #define PCI_CFG_CMD 4 37 #define PCI_CFG_STAT 6 38 #define PCI_CFG_REV 8 39 #define PCI_CFG_PROGIF 9 40 #define PCI_CFG_SUBCL 0xa 41 #define PCI_CFG_BASECL 0xb 42 #define PCI_CFG_CLSZ 0xc 43 #define PCI_CFG_LATTIM 0xd 44 #define PCI_CFG_HDR 0xe 45 #define PCI_CFG_BIST 0xf 46 #define PCI_CFG_BAR0 0x10 47 #define PCI_CFG_BAR1 0x14 48 #define PCI_CFG_BAR2 0x18 49 #define PCI_CFG_BAR3 0x1c 50 #define PCI_CFG_BAR4 0x20 51 #define PCI_CFG_BAR5 0x24 52 #define PCI_CFG_CIS 0x28 53 #define PCI_CFG_SVID 0x2c 54 #define PCI_CFG_SSID 0x2e 55 #define PCI_CFG_ROMBAR 0x30 56 #define PCI_CFG_CAPPTR 0x34 57 #define PCI_CFG_INT 0x3c 58 #define PCI_CFG_PIN 0x3d 59 #define PCI_CFG_MINGNT 0x3e 60 #define PCI_CFG_MAXLAT 0x3f 61 #define PCI_CFG_DEVCTRL 0xd8 62 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ 63 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ 64 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 65 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 66 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 67 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 68 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 69 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 70 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 71 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */ 72 #define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */ 73 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 74 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 75 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 76 77 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 78 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ 79 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ 80 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the 81 * 8KB window, so their address is the "regular" 82 * address plus 4K 83 */ 84 /* 85 * PCIE GEN2 changed some of the above locations for 86 * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase 87 * BAR0 maps 32K of register space 88 */ 89 #define PCIE2_BAR0_WIN2 0x70 /* backplane addres space accessed by second 4KB of BAR0 */ 90 #define PCIE2_BAR0_CORE2_WIN 0x74 /* backplane addres space accessed by second 4KB of BAR0 */ 91 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */ 92 93 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ 94 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 95 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 96 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 97 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 98 99 100 #define PCI_CONFIG_SPACE_SIZE 256 101 #endif /* _h_pcicfg_ */ 102