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Searched refs:ASYNC_BANK0_BASE (Results 1 – 14 of 14) sorted by relevance

/arch/blackfin/mach-bf518/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro
/arch/blackfin/mach-bf527/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro
/arch/blackfin/mach-bf538/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro
/arch/blackfin/mach-bf548/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro
/arch/blackfin/kernel/
Dprocess.c349 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) { in in_async()
352 if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) in in_async()
354 size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr; in in_async()
355 addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE; in in_async()
Dkgdb.c448 if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) in kgdb_validate_break_address()
Dtrace.c85 } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) { in decode_address()
Dsetup.c652 ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32; in memory_setup()
/arch/blackfin/kernel/cplb-mpu/
Dcplbmgr.c122 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { in dcplb_miss()
126 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT; in dcplb_miss()
221 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { in icplb_miss()
226 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT; in icplb_miss()
/arch/blackfin/include/asm/
Dmmu_context.h128 if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)) in protect_page()
129 page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12; in protect_page()
/arch/blackfin/mach-bf537/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro
/arch/blackfin/mach-bf533/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro
/arch/blackfin/kernel/cplb-nompu/
Dcplbinit.c133 dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE; in generate_cplb_tables_all()
172 icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; in generate_cplb_tables_all()
/arch/blackfin/mach-bf561/include/mach/
Dmem_map.h22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ macro