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Searched refs:AT91_PMC_SR (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-at91/
Dpm_slowclock.S57 ldr tmp1, [pmc, #AT91_PMC_SR]
71 ldr tmp1, [pmc, #AT91_PMC_SR]
85 ldr tmp1, [pmc, #AT91_PMC_SR]
99 ldr tmp1, [pmc, #AT91_PMC_SR]
Dclock.c135 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); in pllb_mode()
167 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); in pmc_uckr_mode()
440 sr = at91_pmc_read(AT91_PMC_SR); in at91_clk_show()
/arch/arm/mach-at91/include/mach/
Dat91_pmc.h146 #define AT91_PMC_SR 0x68 /* Status Register */ macro