| /arch/sh/mm/ |
| D | cache-shx3.c | 22 ccr = __raw_readl(CCR); in shx3_cache_init()
43 writel_uncached(ccr, CCR); in shx3_cache_init()
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| D | cache-sh2a.c | 137 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR); in sh2a__flush_invalidate_region()
170 __raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR); in sh2a_flush_icache_range()
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| D | cache-sh2.c | 66 ccr = __raw_readl(CCR); in sh2__flush_invalidate_region()
68 __raw_writel(ccr, CCR); in sh2__flush_invalidate_region()
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| D | cache-debugfs.c | 39 ccr = __raw_readl(CCR); in cache_seq_show()
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| D | cache-sh4.c | 136 ccr = __raw_readl(CCR); in flush_icache_all()
138 __raw_writel(ccr, CCR); in flush_icache_all()
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| D | cache.c | 288 #ifdef CCR in cpu_cache_init()
289 cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE); in cpu_cache_init()
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| /arch/arm/plat-omap/ |
| D | dma.c | 202 ccr = p->dma_read(CCR, lch); in omap_set_dma_priority()
207 p->dma_write(ccr, CCR, lch); in omap_set_dma_priority()
226 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
230 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
242 val = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
267 p->dma_write(val, CCR, lch); in omap_set_dma_transfer_params()
312 val = p->dma_read(CCR, lch); in omap_set_dma_color_mode()
327 p->dma_write(val, CCR, lch); in omap_set_dma_color_mode()
377 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
380 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
[all …]
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| /arch/sh/include/cpu-sh2/cpu/ |
| D | cache.h | 21 #define CCR 0xffffffec macro
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| /arch/sh/include/cpu-sh3/cpu/ |
| D | cache.h | 20 #define CCR 0xffffffec /* Address of Cache Control Register */ macro
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| /arch/sh/include/cpu-sh2a/cpu/ |
| D | cache.h | 20 #define CCR 0xfffc1000 /* CCR1 */ macro
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| /arch/sh/include/cpu-sh4/cpu/ |
| D | cache.h | 20 #define CCR 0xff00001c /* Address of Cache Control Register */ macro
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| /arch/arm/mach-ixp2000/include/mach/ |
| D | platform.h | 74 unsigned long CCR; /* Clock divide */ member
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| /arch/sh/kernel/cpu/ |
| D | init.c | 115 ccr = __raw_readl(CCR); in cache_init()
192 __raw_writel(flags, CCR); in cache_init()
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| /arch/arm/mach-omap1/ |
| D | dma.c | 63 [CCR] = 0x02,
228 l = dma_read(CCR, lch); in omap1_clear_dma()
230 dma_write(l, CCR, lch); in omap1_clear_dma()
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| /arch/arm/mach-ixp2000/ |
| D | core.c | 54 old_cfg->CCR = *IXP2000_SLOWPORT_CCR; in ixp2000_acquire_slowport()
60 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR); in ixp2000_acquire_slowport()
69 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR); in ixp2000_release_slowport()
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| D | ixdp2x00.c | 57 .CCR = SLOWPORT_CCR_DIV_2,
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| /arch/cris/arch-v10/kernel/ |
| D | kgdb.c | 387 P4, CCR, P6, MOF, enumerator
570 else if (regno == CCR) { in write_register()
573 hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short), in write_register()
642 else if (regno == P4 || regno == CCR) { in read_register()
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| /arch/arm/mach-omap2/ |
| D | dma.c | 63 [CCR] = 0x80,
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| /arch/frv/mm/ |
| D | tlb-miss.S | 46 # SCR2 - saved CCR
91 # SCR2 - saved CCR
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| /arch/arm/plat-omap/include/plat/ |
| D | dma.h | 330 CSDP, CCR, CICR, CSR, enumerator
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| /arch/blackfin/include/asm/ |
| D | bfin_can.h | 117 #define CCR 0x0080 /* CAN Configuration Mode Request */ macro
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| /arch/arm/mach-imx/ |
| D | clock-imx6q.c | 65 #define CCR (CCM_BASE + 0x00) macro
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