Searched refs:CKSEG1ADDR (Results 1 – 25 of 35) sorted by relevance
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38 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)44 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)45 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)46 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)47 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)48 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)49 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)50 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)51 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)52 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)[all …]
74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
115 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
73 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn01()81 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn230()90 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); in prom_init_kn02()99 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn02xa()100 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn02xa()109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn03()110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn03()
147 (void *)CKSEG1ADDR(address); in dec_ecc_be_backend()230 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init()232 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); in dec_kn02_be_init()233 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); in dec_kn02_be_init()248 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init()249 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn03_be_init()251 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); in dec_kn03_be_init()252 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); in dec_kn03_be_init()
32 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_ack()33 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); in dec_kn02xa_be_ack()43 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_backend()44 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); in dec_kn02xa_be_backend()129 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn02xa_be_init()
34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq()43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq()66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs()
53 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack()66 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + in dec_kn01_be_backend()154 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt()181 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init()
16 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); in back_to_prom()
29 #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)30 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)31 #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
47 usp = CKSEG1ADDR(sp); in run_uncached()59 ufunc = CKSEG1ADDR(lfunc); in run_uncached()
25 #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
53 #define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */132 li t0, CKSEG1ADDR(RESET_DATA_PHYS)201 li t0, CKSEG1ADDR(RESET_VEC_PHYS)258 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
242 reset_vec = CKSEG1ADDR(RESET_VEC_PHYS); in nlm_wakeup_secondary_cpus()250 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); in nlm_wakeup_secondary_cpus()
9 #define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
19 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
38 .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
82 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); in plat_mem_setup()
63 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); in nlm_set_nmi_handler()
33 #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)84 return (void *)CKSEG1ADDR(hwconf); in prom_get_hwconf()
38 #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
57 #define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
57 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); in nlm_hal_init()
285 ptr32 = (void *)CKSEG1ADDR(addr); in ip22_gio_id()295 ptr8 = (void *)CKSEG1ADDR(addr + 3); in ip22_gio_id()297 ptr16 = (void *)CKSEG1ADDR(addr + 2); in ip22_gio_id()318 ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); in ip22_is_gr2()