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Searched refs:CLK_PLL (Results 1 – 12 of 12) sorted by relevance

/arch/c6x/platforms/
Dplldata.c43 .flags = CLK_PLL,
48 .flags = CLK_PLL,
53 .flags = CLK_PLL,
58 .flags = CLK_PLL,
63 .flags = CLK_PLL,
68 .flags = CLK_PLL,
73 .flags = CLK_PLL,
78 .flags = CLK_PLL,
83 .flags = CLK_PLL,
88 .flags = CLK_PLL,
[all …]
Dpll.c339 else if (clk->flags & CLK_PLL) in __init_clk()
386 if (parent->flags & CLK_PLL) in dump_clock()
/arch/arm/mach-davinci/
Ddm365.c79 .flags = CLK_PLL,
86 .flags = CLK_PLL | PRE_PLL,
92 .flags = CLK_PLL | PRE_PLL,
99 .flags = CLK_PLL | PRE_PLL,
105 .flags = CLK_PLL,
112 .flags = CLK_PLL,
119 .flags = CLK_PLL,
126 .flags = CLK_PLL,
133 .flags = CLK_PLL,
140 .flags = CLK_PLL,
[all …]
Ddm646x.c79 .flags = CLK_PLL,
85 .flags = CLK_PLL,
92 .flags = CLK_PLL,
99 .flags = CLK_PLL,
106 .flags = CLK_PLL,
113 .flags = CLK_PLL,
120 .flags = CLK_PLL,
127 .flags = CLK_PLL,
134 .flags = CLK_PLL,
141 .flags = CLK_PLL | PRE_PLL,
[all …]
Ddm644x.c64 .flags = CLK_PLL,
70 .flags = CLK_PLL,
77 .flags = CLK_PLL,
84 .flags = CLK_PLL,
91 .flags = CLK_PLL,
98 .flags = CLK_PLL | PRE_PLL,
104 .flags = CLK_PLL | PRE_PLL,
112 .flags = CLK_PLL,
118 .flags = CLK_PLL,
125 .flags = CLK_PLL,
[all …]
Ddm355.c65 .flags = CLK_PLL,
72 .flags = CLK_PLL | PRE_PLL,
78 .flags = CLK_PLL,
85 .flags = CLK_PLL,
92 .flags = CLK_PLL,
99 .flags = CLK_PLL,
106 .flags = CLK_PLL | PRE_PLL,
143 .flags = CLK_PLL,
150 .flags = CLK_PLL,
157 .flags = CLK_PLL | PRE_PLL,
Dda850.c69 .flags = CLK_PLL,
76 .flags = CLK_PLL | PRE_PLL,
82 .flags = CLK_PLL,
89 .flags = CLK_PLL,
98 .flags = CLK_PLL,
105 .flags = CLK_PLL,
112 .flags = CLK_PLL,
119 .flags = CLK_PLL,
133 .flags = CLK_PLL,
139 .flags = CLK_PLL | PRE_PLL,
[all …]
Dclock.h111 #define CLK_PLL BIT(3) /* PLL-derived clock */ macro
Dda830.c55 .flags = CLK_PLL,
61 .flags = CLK_PLL | PRE_PLL,
67 .flags = CLK_PLL,
74 .flags = CLK_PLL,
81 .flags = CLK_PLL,
88 .flags = CLK_PLL,
95 .flags = CLK_PLL,
102 .flags = CLK_PLL,
Dclock.c47 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && in __clk_disable()
554 else if (clk->flags & CLK_PLL) in davinci_clk_init()
610 if (parent->flags & CLK_PLL) in dump_clock()
Dtnetv107x.c126 .flags = CLK_PLL, \
139 .flags = CLK_PLL, \
/arch/c6x/include/asm/
Dclock.h101 #define CLK_PLL BIT(2) /* PLL-derived clock */ macro