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Searched refs:CP0_ENTRYLO0 (Results 1 – 2 of 2) sorted by relevance

/arch/mips/kernel/
Dhead.S54 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
/arch/mips/include/asm/
Dmipsregs.h45 #define CP0_ENTRYLO0 $2 macro