1 /*
2 * TI DaVinci DM365 EVM board support
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
19 #include <linux/io.h>
20 #include <linux/clk.h>
21 #include <linux/i2c/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/input.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/eeprom.h>
30
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33
34 #include <mach/mux.h>
35 #include <mach/common.h>
36 #include <mach/i2c.h>
37 #include <mach/serial.h>
38 #include <mach/mmc.h>
39 #include <mach/nand.h>
40 #include <mach/keyscan.h>
41
42 #include <media/tvp514x.h>
43
44 #include "davinci.h"
45
have_imager(void)46 static inline int have_imager(void)
47 {
48 /* REVISIT when it's supported, trigger via Kconfig */
49 return 0;
50 }
51
have_tvp7002(void)52 static inline int have_tvp7002(void)
53 {
54 /* REVISIT when it's supported, trigger via Kconfig */
55 return 0;
56 }
57
58 #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
59 /*
60 * A MAX-II CPLD is used for various board control functions.
61 */
62 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
63
64 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
65 #define CPLD_TEST CPLD_OFFSET(0,1)
66 #define CPLD_LEDS CPLD_OFFSET(0,2)
67 #define CPLD_MUX CPLD_OFFSET(0,3)
68 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
69 #define CPLD_POWER CPLD_OFFSET(1,1)
70 #define CPLD_VIDEO CPLD_OFFSET(1,2)
71 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
72
73 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
74 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
75
76 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
77 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
78 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
79 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
80 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
81 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
82 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
83 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
84 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
85
86 #define CPLD_RESETS CPLD_OFFSET(4,3)
87
88 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
89 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
90 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
91 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
92 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
93 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
94
95 static void __iomem *cpld;
96
97
98 /* NOTE: this is geared for the standard config, with a socketed
99 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
100 * swap chips with a different block size, partitioning will
101 * need to be changed. This NAND chip MT29F16G08FAA is the default
102 * NAND shipped with the Spectrum Digital DM365 EVM
103 */
104 #define NAND_BLOCK_SIZE SZ_128K
105
106 static struct mtd_partition davinci_nand_partitions[] = {
107 {
108 /* UBL (a few copies) plus U-Boot */
109 .name = "bootloader",
110 .offset = 0,
111 .size = 30 * NAND_BLOCK_SIZE,
112 .mask_flags = MTD_WRITEABLE, /* force read-only */
113 }, {
114 /* U-Boot environment */
115 .name = "params",
116 .offset = MTDPART_OFS_APPEND,
117 .size = 2 * NAND_BLOCK_SIZE,
118 .mask_flags = 0,
119 }, {
120 .name = "kernel",
121 .offset = MTDPART_OFS_APPEND,
122 .size = SZ_4M,
123 .mask_flags = 0,
124 }, {
125 .name = "filesystem1",
126 .offset = MTDPART_OFS_APPEND,
127 .size = SZ_512M,
128 .mask_flags = 0,
129 }, {
130 .name = "filesystem2",
131 .offset = MTDPART_OFS_APPEND,
132 .size = MTDPART_SIZ_FULL,
133 .mask_flags = 0,
134 }
135 /* two blocks with bad block table (and mirror) at the end */
136 };
137
138 static struct davinci_nand_pdata davinci_nand_data = {
139 .mask_chipsel = BIT(14),
140 .parts = davinci_nand_partitions,
141 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
142 .ecc_mode = NAND_ECC_HW,
143 .bbt_options = NAND_BBT_USE_FLASH,
144 .ecc_bits = 4,
145 };
146
147 static struct resource davinci_nand_resources[] = {
148 {
149 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
150 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
151 .flags = IORESOURCE_MEM,
152 }, {
153 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
154 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
155 .flags = IORESOURCE_MEM,
156 },
157 };
158
159 static struct platform_device davinci_nand_device = {
160 .name = "davinci_nand",
161 .id = 0,
162 .num_resources = ARRAY_SIZE(davinci_nand_resources),
163 .resource = davinci_nand_resources,
164 .dev = {
165 .platform_data = &davinci_nand_data,
166 },
167 };
168
169 static struct at24_platform_data eeprom_info = {
170 .byte_len = (256*1024) / 8,
171 .page_size = 64,
172 .flags = AT24_FLAG_ADDR16,
173 .setup = davinci_get_mac_addr,
174 .context = (void *)0x7f00,
175 };
176
177 static struct snd_platform_data dm365_evm_snd_data = {
178 .asp_chan_q = EVENTQ_3,
179 };
180
181 static struct i2c_board_info i2c_info[] = {
182 {
183 I2C_BOARD_INFO("24c256", 0x50),
184 .platform_data = &eeprom_info,
185 },
186 {
187 I2C_BOARD_INFO("tlv320aic3x", 0x18),
188 },
189 };
190
191 static struct davinci_i2c_platform_data i2c_pdata = {
192 .bus_freq = 400 /* kHz */,
193 .bus_delay = 0 /* usec */,
194 };
195
dm365evm_keyscan_enable(struct device * dev)196 static int dm365evm_keyscan_enable(struct device *dev)
197 {
198 return davinci_cfg_reg(DM365_KEYSCAN);
199 }
200
201 static unsigned short dm365evm_keymap[] = {
202 KEY_KP2,
203 KEY_LEFT,
204 KEY_EXIT,
205 KEY_DOWN,
206 KEY_ENTER,
207 KEY_UP,
208 KEY_KP1,
209 KEY_RIGHT,
210 KEY_MENU,
211 KEY_RECORD,
212 KEY_REWIND,
213 KEY_KPMINUS,
214 KEY_STOP,
215 KEY_FASTFORWARD,
216 KEY_KPPLUS,
217 KEY_PLAYPAUSE,
218 0
219 };
220
221 static struct davinci_ks_platform_data dm365evm_ks_data = {
222 .device_enable = dm365evm_keyscan_enable,
223 .keymap = dm365evm_keymap,
224 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
225 .rep = 1,
226 /* Scan period = strobe + interval */
227 .strobe = 0x5,
228 .interval = 0x2,
229 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
230 };
231
cpld_mmc_get_cd(int module)232 static int cpld_mmc_get_cd(int module)
233 {
234 if (!cpld)
235 return -ENXIO;
236
237 /* low == card present */
238 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
239 }
240
cpld_mmc_get_ro(int module)241 static int cpld_mmc_get_ro(int module)
242 {
243 if (!cpld)
244 return -ENXIO;
245
246 /* high == card's write protect switch active */
247 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
248 }
249
250 static struct davinci_mmc_config dm365evm_mmc_config = {
251 .get_cd = cpld_mmc_get_cd,
252 .get_ro = cpld_mmc_get_ro,
253 .wires = 4,
254 .max_freq = 50000000,
255 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
256 .version = MMC_CTLR_VERSION_2,
257 };
258
dm365evm_emac_configure(void)259 static void dm365evm_emac_configure(void)
260 {
261 /*
262 * EMAC pins are multiplexed with GPIO and UART
263 * Further details are available at the DM365 ARM
264 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
265 */
266 davinci_cfg_reg(DM365_EMAC_TX_EN);
267 davinci_cfg_reg(DM365_EMAC_TX_CLK);
268 davinci_cfg_reg(DM365_EMAC_COL);
269 davinci_cfg_reg(DM365_EMAC_TXD3);
270 davinci_cfg_reg(DM365_EMAC_TXD2);
271 davinci_cfg_reg(DM365_EMAC_TXD1);
272 davinci_cfg_reg(DM365_EMAC_TXD0);
273 davinci_cfg_reg(DM365_EMAC_RXD3);
274 davinci_cfg_reg(DM365_EMAC_RXD2);
275 davinci_cfg_reg(DM365_EMAC_RXD1);
276 davinci_cfg_reg(DM365_EMAC_RXD0);
277 davinci_cfg_reg(DM365_EMAC_RX_CLK);
278 davinci_cfg_reg(DM365_EMAC_RX_DV);
279 davinci_cfg_reg(DM365_EMAC_RX_ER);
280 davinci_cfg_reg(DM365_EMAC_CRS);
281 davinci_cfg_reg(DM365_EMAC_MDIO);
282 davinci_cfg_reg(DM365_EMAC_MDCLK);
283
284 /*
285 * EMAC interrupts are multiplexed with GPIO interrupts
286 * Details are available at the DM365 ARM
287 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
288 */
289 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
290 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
291 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
292 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
293 }
294
dm365evm_mmc_configure(void)295 static void dm365evm_mmc_configure(void)
296 {
297 /*
298 * MMC/SD pins are multiplexed with GPIO and EMIF
299 * Further details are available at the DM365 ARM
300 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
301 */
302 davinci_cfg_reg(DM365_SD1_CLK);
303 davinci_cfg_reg(DM365_SD1_CMD);
304 davinci_cfg_reg(DM365_SD1_DATA3);
305 davinci_cfg_reg(DM365_SD1_DATA2);
306 davinci_cfg_reg(DM365_SD1_DATA1);
307 davinci_cfg_reg(DM365_SD1_DATA0);
308 }
309
310 static struct tvp514x_platform_data tvp5146_pdata = {
311 .clk_polarity = 0,
312 .hs_polarity = 1,
313 .vs_polarity = 1
314 };
315
316 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
317 /* Inputs available at the TVP5146 */
318 static struct v4l2_input tvp5146_inputs[] = {
319 {
320 .index = 0,
321 .name = "Composite",
322 .type = V4L2_INPUT_TYPE_CAMERA,
323 .std = TVP514X_STD_ALL,
324 },
325 {
326 .index = 1,
327 .name = "S-Video",
328 .type = V4L2_INPUT_TYPE_CAMERA,
329 .std = TVP514X_STD_ALL,
330 },
331 };
332
333 /*
334 * this is the route info for connecting each input to decoder
335 * ouput that goes to vpfe. There is a one to one correspondence
336 * with tvp5146_inputs
337 */
338 static struct vpfe_route tvp5146_routes[] = {
339 {
340 .input = INPUT_CVBS_VI2B,
341 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
342 },
343 {
344 .input = INPUT_SVIDEO_VI2C_VI1C,
345 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
346 },
347 };
348
349 static struct vpfe_subdev_info vpfe_sub_devs[] = {
350 {
351 .name = "tvp5146",
352 .grp_id = 0,
353 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
354 .inputs = tvp5146_inputs,
355 .routes = tvp5146_routes,
356 .can_route = 1,
357 .ccdc_if_params = {
358 .if_type = VPFE_BT656,
359 .hdpol = VPFE_PINPOL_POSITIVE,
360 .vdpol = VPFE_PINPOL_POSITIVE,
361 },
362 .board_info = {
363 I2C_BOARD_INFO("tvp5146", 0x5d),
364 .platform_data = &tvp5146_pdata,
365 },
366 },
367 };
368
369 static struct vpfe_config vpfe_cfg = {
370 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
371 .sub_devs = vpfe_sub_devs,
372 .i2c_adapter_id = 1,
373 .card_name = "DM365 EVM",
374 .ccdc = "ISIF",
375 };
376
evm_init_i2c(void)377 static void __init evm_init_i2c(void)
378 {
379 davinci_init_i2c(&i2c_pdata);
380 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
381 }
382
383 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
384 &davinci_nand_device,
385 };
386
have_leds(void)387 static inline int have_leds(void)
388 {
389 #ifdef CONFIG_LEDS_CLASS
390 return 1;
391 #else
392 return 0;
393 #endif
394 }
395
396 struct cpld_led {
397 struct led_classdev cdev;
398 u8 mask;
399 };
400
401 static const struct {
402 const char *name;
403 const char *trigger;
404 } cpld_leds[] = {
405 { "dm365evm::ds2", },
406 { "dm365evm::ds3", },
407 { "dm365evm::ds4", },
408 { "dm365evm::ds5", },
409 { "dm365evm::ds6", "nand-disk", },
410 { "dm365evm::ds7", "mmc1", },
411 { "dm365evm::ds8", "mmc0", },
412 { "dm365evm::ds9", "heartbeat", },
413 };
414
cpld_led_set(struct led_classdev * cdev,enum led_brightness b)415 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
416 {
417 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
418 u8 reg = __raw_readb(cpld + CPLD_LEDS);
419
420 if (b != LED_OFF)
421 reg &= ~led->mask;
422 else
423 reg |= led->mask;
424 __raw_writeb(reg, cpld + CPLD_LEDS);
425 }
426
cpld_led_get(struct led_classdev * cdev)427 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
428 {
429 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
430 u8 reg = __raw_readb(cpld + CPLD_LEDS);
431
432 return (reg & led->mask) ? LED_OFF : LED_FULL;
433 }
434
cpld_leds_init(void)435 static int __init cpld_leds_init(void)
436 {
437 int i;
438
439 if (!have_leds() || !cpld)
440 return 0;
441
442 /* setup LEDs */
443 __raw_writeb(0xff, cpld + CPLD_LEDS);
444 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
445 struct cpld_led *led;
446
447 led = kzalloc(sizeof(*led), GFP_KERNEL);
448 if (!led)
449 break;
450
451 led->cdev.name = cpld_leds[i].name;
452 led->cdev.brightness_set = cpld_led_set;
453 led->cdev.brightness_get = cpld_led_get;
454 led->cdev.default_trigger = cpld_leds[i].trigger;
455 led->mask = BIT(i);
456
457 if (led_classdev_register(NULL, &led->cdev) < 0) {
458 kfree(led);
459 break;
460 }
461 }
462
463 return 0;
464 }
465 /* run after subsys_initcall() for LEDs */
466 fs_initcall(cpld_leds_init);
467
468
evm_init_cpld(void)469 static void __init evm_init_cpld(void)
470 {
471 u8 mux, resets;
472 const char *label;
473 struct clk *aemif_clk;
474
475 /* Make sure we can configure the CPLD through CS1. Then
476 * leave it on for later access to MMC and LED registers.
477 */
478 aemif_clk = clk_get(NULL, "aemif");
479 if (IS_ERR(aemif_clk))
480 return;
481 clk_enable(aemif_clk);
482
483 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
484 "cpld") == NULL)
485 goto fail;
486 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
487 if (!cpld) {
488 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
489 SECTION_SIZE);
490 fail:
491 pr_err("ERROR: can't map CPLD\n");
492 clk_disable(aemif_clk);
493 return;
494 }
495
496 /* External muxing for some signals */
497 mux = 0;
498
499 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
500 * NOTE: SW4 bus width setting must match!
501 */
502 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
503 /* external keypad mux */
504 mux |= BIT(7);
505
506 platform_add_devices(dm365_evm_nand_devices,
507 ARRAY_SIZE(dm365_evm_nand_devices));
508 } else {
509 /* no OneNAND support yet */
510 }
511
512 /* Leave external chips in reset when unused. */
513 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
514
515 /* Static video input config with SN74CBT16214 1-of-3 mux:
516 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
517 * - port b2 == imager (mux lowbits == 2 or 7)
518 * - port b3 == tvp5146 (mux lowbits == 5)
519 *
520 * Runtime switching could work too, with limitations.
521 */
522 if (have_imager()) {
523 label = "HD imager";
524 mux |= 2;
525
526 /* externally mux MMC1/ENET/AIC33 to imager */
527 mux |= BIT(6) | BIT(5) | BIT(3);
528 } else {
529 struct davinci_soc_info *soc_info = &davinci_soc_info;
530
531 /* we can use MMC1 ... */
532 dm365evm_mmc_configure();
533 davinci_setup_mmc(1, &dm365evm_mmc_config);
534
535 /* ... and ENET ... */
536 dm365evm_emac_configure();
537 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
538 resets &= ~BIT(3);
539
540 /* ... and AIC33 */
541 resets &= ~BIT(1);
542
543 if (have_tvp7002()) {
544 mux |= 1;
545 resets &= ~BIT(2);
546 label = "tvp7002 HD";
547 } else {
548 /* default to tvp5146 */
549 mux |= 5;
550 resets &= ~BIT(0);
551 label = "tvp5146 SD";
552 }
553 }
554 __raw_writeb(mux, cpld + CPLD_MUX);
555 __raw_writeb(resets, cpld + CPLD_RESETS);
556 pr_info("EVM: %s video input\n", label);
557
558 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
559 }
560
561 static struct davinci_uart_config uart_config __initdata = {
562 .enabled_uarts = (1 << 0),
563 };
564
dm365_evm_map_io(void)565 static void __init dm365_evm_map_io(void)
566 {
567 /* setup input configuration for VPFE input devices */
568 dm365_set_vpfe_config(&vpfe_cfg);
569 dm365_init();
570 }
571
572 static struct spi_eeprom at25640 = {
573 .byte_len = SZ_64K / 8,
574 .name = "at25640",
575 .page_size = 32,
576 .flags = EE_ADDR2,
577 };
578
579 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
580 {
581 .modalias = "at25",
582 .platform_data = &at25640,
583 .max_speed_hz = 10 * 1000 * 1000,
584 .bus_num = 0,
585 .chip_select = 0,
586 .mode = SPI_MODE_0,
587 },
588 };
589
dm365_evm_init(void)590 static __init void dm365_evm_init(void)
591 {
592 evm_init_i2c();
593 davinci_serial_init(&uart_config);
594
595 dm365evm_emac_configure();
596 dm365evm_mmc_configure();
597
598 davinci_setup_mmc(0, &dm365evm_mmc_config);
599
600 /* maybe setup mmc1/etc ... _after_ mmc0 */
601 evm_init_cpld();
602
603 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
604 dm365_init_asp(&dm365_evm_snd_data);
605 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
606 dm365_init_vc(&dm365_evm_snd_data);
607 #endif
608 dm365_init_rtc();
609 dm365_init_ks(&dm365evm_ks_data);
610
611 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
612 ARRAY_SIZE(dm365_evm_spi_info));
613 }
614
615 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
616 .atag_offset = 0x100,
617 .map_io = dm365_evm_map_io,
618 .init_irq = davinci_irq_init,
619 .timer = &davinci_timer,
620 .init_machine = dm365_evm_init,
621 .dma_zone_size = SZ_128M,
622 .restart = davinci_restart,
623 MACHINE_END
624
625