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Searched refs:CSR_TIMER1_LOAD (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-footbridge/
Ddc21285-timer.c56 *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); in ckevt_dc21285_set_mode()
/arch/arm/include/asm/hardware/
Ddec21285.h123 #define CSR_TIMER1_LOAD DC21285_IO(0x0300) macro