Searched refs:DDR2 (Results 1 – 8 of 8) sorted by relevance
23 hex "DDR2 MRS"27 hex "DDR2 SDRAM timing"33 hex "DDR2 config"37 hex "DDR2 latency"
78 @ DDR2 BaseAddr99 @ prepare DDR2 refresh settings120 @ put DDR2 into self-refresh
50 reg = <0x0 0x20000000 // DDR2 512M at 0
317 tristate "Axon DDR2 memory device driver"321 It registers one block device per Axon's DDR2 memory bank found
135 mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which
883 DDR2 = 1, /**< DDR2 */ enumerator
204 By default, 2, i.e. 2^2 == 4 DDR2 controllers.
1227 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller