Searched refs:DDRPhaseCtrl1 (Results 1 – 2 of 2) sorted by relevance
1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; in chipcHw_ddrSwPhaseAlignEnable()1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; in chipcHw_ddrSwPhaseAlignDisable()1310 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE; in chipcHw_ddrHwPhaseAlignEnable()1323 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE; in chipcHw_ddrHwPhaseAlignDisable()1409 pChipcHw->DDRPhaseCtrl1 &= in chipcHw_setDdrHwPhaseAlignMargin()1415 pChipcHw->DDRPhaseCtrl1 |= in chipcHw_setDdrHwPhaseAlignMargin()
84 uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */ member