Searched refs:DDRPhaseCtrl2 (Results 1 – 2 of 2) sorted by relevance
1558 pChipcHw->DDRPhaseCtrl2 &= in chipcHw_ddrHwPhaseAlignTimeout()1561 pChipcHw->DDRPhaseCtrl2 |= in chipcHw_ddrHwPhaseAlignTimeout()1597 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED; in chipcHw_ddrHwPhaseAlignTimeoutInterruptClear()1598 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED; in chipcHw_ddrHwPhaseAlignTimeoutInterruptClear()1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; in chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable()1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; in chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable()
88 uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */ member