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Searched refs:DIV_U71_FIXED (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-tegra/
Dclock.h31 #define DIV_U71_FIXED (1 << 2) macro
Dtegra2_clocks.c859 if (c->flags & DIV_U71_FIXED) in tegra2_pll_div_clk_set_rate()
1596 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1606 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1616 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1626 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
Dtegra30_clocks.c1352 if (c->flags & DIV_U71_FIXED) in tegra30_pll_div_clk_set_rate()
2187 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2197 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2207 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2217 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,