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Searched refs:DIV_U71_INT (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-tegra/
Dclock.h50 #define DIV_U71_INT (1 << 21) macro
Dtegra30_clocks.c437 if (!(flags & DIV_U71_INT)) in clk_div71_get_divider()
442 if (flags & DIV_U71_INT) in clk_div71_get_divider()
2807 .flags = DIV_U71 | DIV_U71_INT,
2916 …("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2937 … "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_…
2938 … NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE …
2939 … NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE …
2940 … NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
2942 …("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2943 …("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
[all …]