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Searched refs:DMA1_5_CONFIG (Results 1 – 2 of 2) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h383 #define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ macro
DcdefBF561.h657 #define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
658 #define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)