Searched refs:EXCSAVE_1 (Results 1 – 7 of 7) sorted by relevance
/arch/xtensa/kernel/ |
D | vectors.S | 72 xsr a3, EXCSAVE_1 # save a3 and get dispatch table 96 xsr a3, EXCSAVE_1 # save a3, and get dispatch table 208 wsr a3, EXCSAVE_1 # save a3 257 wsr a3, EXCSAVE_1 # save a3 334 rsr a3, EXCSAVE_1 335 wsr a0, EXCSAVE_1
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D | entry.S | 115 xsr a3, EXCSAVE_1 255 xsr a3, EXCSAVE_1 # restore a3, excsave_1 689 2: rsr a2, EXCSAVE_1 807 xsr a3, EXCSAVE_1 # make sure excsave_1 is valid for dbl. 823 wsr a0, EXCSAVE_1 992 rsr a3, EXCSAVE_1 994 wsr a0, EXCSAVE_1 1050 xsr a3, EXCSAVE_1 # restore a3, excsave1 1133 xsr a3, EXCSAVE_1 # restore a3 and excsave_1 1185 rsr a3, EXCSAVE_1 # get spill-mask [all …]
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D | head.S | 68 wsr a2, EXCSAVE_1 220 xsr a6, EXCSAVE_1
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D | coprocessor.S | 46 wsr a0, EXCSAVE_1 223 wsr a0, EXCSAVE_1 232 xsr a3, EXCSAVE_1
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D | align.S | 174 xsr a3, EXCSAVE_1 409 rsr a3, EXCSAVE_1
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D | traps.c | 342 __asm__ __volatile__("wsr %0, "__stringify(EXCSAVE_1)"\n" : : "a" (i)); in trap_init()
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/arch/xtensa/include/asm/ |
D | regs.h | 56 #define EXCSAVE_1 209 macro
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