| /arch/sparc/include/asm/ |
| D | visasm.h | 16 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
22 297: wr %g0, FPRS_FEF, %fprs; \
32 andcc %o5, FPRS_FEF, %g0; \
39 297: wr %o5, FPRS_FEF, %fprs; \
57 " " : : "i" (FPRS_FEF|FPRS_DU) : in save_and_clear_fpu()
|
| D | pstate.h | 74 #define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */ macro
|
| /arch/sparc/lib/ |
| D | VISsave.S | 91 wr %g0, FPRS_FEF, %fprs
112 wr %g0, FPRS_FEF, %fprs
144 wr %o5, FPRS_FEF, %fprs
|
| D | U3memcpy.S | 12 #define FPRS_FEF 0x04 macro
14 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
16 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
18 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
19 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
|
| D | xor.S | 29 andcc %o5, FPRS_FEF|FPRS_DU, %g0
34 0: wr %g0, FPRS_FEF, %fprs
100 andcc %o5, FPRS_FEF|FPRS_DU, %g0
105 0: wr %g0, FPRS_FEF, %fprs
168 andcc %o5, FPRS_FEF|FPRS_DU, %g0
173 0: wr %g0, FPRS_FEF, %fprs
256 andcc %o5, FPRS_FEF|FPRS_DU, %g0
261 0: wr %g0, FPRS_FEF, %fprs
|
| D | NG2memcpy.S | 14 #define FPRS_FEF 0x04 macro
16 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
18 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
20 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
21 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
|
| D | U1memcpy.S | 14 #define FPRS_FEF 0x04 macro
16 #define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
18 #define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
20 #define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
21 #define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
|
| /arch/sparc/kernel/ |
| D | rtrap_64.S | 37 andcc %l5, FPRS_FEF, %g0
334 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
337 andcc %l2, FPRS_FEF, %g0
342 wr %g1, FPRS_FEF, %fprs
366 5: wr %g0, FPRS_FEF, %fprs
|
| D | unaligned_64.c | 527 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in handle_ldf_stq()
528 current_thread_info()->fpsaved[0] = FPRS_FEF; in handle_ldf_stq()
608 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in handle_lddfmna()
609 current_thread_info()->fpsaved[0] = FPRS_FEF; in handle_lddfmna()
|
| D | fpu_traps.S | 11 andcc %g5, FPRS_FEF, %g0
24 wr %g0, FPRS_FEF, %fprs
25 andcc %g5, FPRS_FEF, %g0
191 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
|
| D | ptrace_64.c | 365 if (fprs & FPRS_FEF) { in fpregs64_get()
429 fprs |= (FPRS_FEF | FPRS_DL | FPRS_DU); in fpregs64_set()
715 if (fprs & FPRS_FEF) { in fpregs32_get()
791 fprs |= (FPRS_FEF | FPRS_DL); in fpregs32_set()
|
| D | signal_64.c | 158 fenab = (current_thread_info()->fpsaved[0] & FPRS_FEF); in sparc64_get_context()
387 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame()
402 if (current_thread_info()->fpsaved[0] & FPRS_FEF) { in setup_rt_frame()
|
| D | signal32.c | 500 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_frame32()
522 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_frame32()
642 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame32()
664 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame32()
|
| D | process_64.c | 686 if (fprs & FPRS_FEF) { in dump_fpu()
706 if(fprs & FPRS_FEF) { in dump_fpu()
|
| D | prom_irqtrans.c | 365 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
|
| /arch/sparc/math-emu/ |
| D | math_64.c | 409 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in do_mathemu()
410 current_thread_info()->fpsaved[0] = FPRS_FEF; in do_mathemu()
|