/arch/mips/include/asm/lasat/ |
D | lasatint.h | 5 #define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) 6 #define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) 10 #define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) 11 #define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
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D | picvue.h | 2 #define PVC_REG_100 KSEG1ADDR(0x1c820000) 10 #define PVC_REG_200 KSEG1ADDR(0x11000000)
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D | eeprom.h | 4 #define AT93C_REG_100 KSEG1ADDR(0x1c810000) 12 #define AT93C_REG_200 KSEG1ADDR(0x11000000)
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D | ds1603.h | 4 #define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) 11 #define DS1603_REG_200 (KSEG1ADDR(0x11000000))
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/arch/mips/include/asm/mach-ar7/ |
D | ar7.h | 124 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == in ar7_is_titan() 131 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); in ar7_chip_id() 136 unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + in titan_chip_id() 143 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : in ar7_chip_rev() 170 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL); in ar7_device_enable() 178 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL); in ar7_device_disable() 191 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); in ar7_device_on() 198 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); in ar7_device_off()
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/arch/mips/lasat/ |
D | setup.c | 59 .reset_reg = (void *)KSEG1ADDR(0x1c840000), 60 .flash_wp_reg = (void *)KSEG1ADDR(0x1c800000), 2 62 .reset_reg = (void *)KSEG1ADDR(0x11080000), 63 .flash_wp_reg = (void *)KSEG1ADDR(0x11000000), 6
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D | serial.c | 50 lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100); in lasat_uart_add() 62 lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_200); in lasat_uart_add()
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/arch/mips/wrppmc/ |
D | setup.c | 22 unsigned long gt64120_base = KSEG1ADDR(0x14000000); 27 (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE); 58 (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE); in wrppmc_early_putc()
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/arch/mips/ath79/ |
D | early_printk.c | 36 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); in prom_putchar_ar71xx() 45 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); in prom_putchar_ar933x() 64 base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE)); in prom_putchar_init()
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/arch/mips/alchemy/common/ |
D | irq.c | 291 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_unmask() 301 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_unmask() 311 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_mask() 321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_mask() 331 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_ack() 345 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_ack() 359 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_maskack() 371 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_maskack() 439 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic_settype() 443 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic_settype() [all …]
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/arch/mips/lantiq/ |
D | setup.c | 25 char **envp = (char **) KSEG1ADDR(fw_arg2); in plat_mem_setup() 35 char *e = (char *)KSEG1ADDR(*envp); in plat_mem_setup()
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D | prom.c | 45 char **argv = (char **) KSEG1ADDR(fw_arg1); in prom_init_cmdline() 49 char *p = (char *) KSEG1ADDR(argv[i]); in prom_init_cmdline()
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D | early_printk.c | 16 #define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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/arch/mips/rb532/ |
D | irq.c | 63 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)}, 66 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)}, 69 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)}, 72 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)}, 75 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
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D | serial.c | 44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
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/arch/mips/ar7/ |
D | memory.c | 38 u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4); in memsize() 39 u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end)); in memsize()
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/arch/mips/include/asm/mach-au1x00/ |
D | gpio-au1000.h | 220 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); in alchemy_gpio1_set_value() 229 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); in alchemy_gpio1_get_value() 236 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); in alchemy_gpio1_direction_input() 280 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in __alchemy_gpio2_mod_dir() 294 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_set_value() 303 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_get_value() 354 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in __alchemy_gpio2_mod_int() 436 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_enable() 450 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_disable()
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/arch/m32r/include/asm/ |
D | addrspace.h | 47 #define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) macro 52 #define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) macro
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/arch/mips/bcm47xx/ |
D | nvram.c | 63 KSEG1ADDR(base + off - NVRAM_SPACE); in early_nvram_init() 70 header = (struct nvram_header *) KSEG1ADDR(base + 4096); in early_nvram_init() 74 header = (struct nvram_header *) KSEG1ADDR(base + 1024); in early_nvram_init()
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/arch/mips/emma/markeins/ |
D | platform.c | 109 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), 117 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), 125 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
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/arch/mips/pci/ |
D | ops-vr41xx.c | 32 #define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14) 33 #define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
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/arch/mips/include/asm/mach-lasat/ |
D | mach-gt64120.h | 14 #define GT64120_BASE (KSEG1ADDR(0x14000000))
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/arch/mips/vr41xx/ibm-workpad/ |
D | setup.c | 29 #define WORKPAD_IO_PORT_BASE KSEG1ADDR(WORKPAD_ISA_IO_BASE)
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/arch/mips/vr41xx/casio-e55/ |
D | setup.c | 29 #define E55_IO_PORT_BASE KSEG1ADDR(E55_ISA_IO_BASE)
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/arch/mips/alchemy/devboards/ |
D | db1550.c | 53 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); in db1550_hw_setup() 460 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); in db1550_dev_init() 463 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); in db1550_dev_init() 467 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); in db1550_dev_init() 470 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); in db1550_dev_init()
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