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1 /*
2  *  This program is free software; you can redistribute it and/or modify
3  *  it under the terms of the GNU General Public License as published by
4  *  the Free Software Foundation; either version 2 of the License, or
5  *  (at your option) any later version.
6  *
7  *  This program is distributed in the hope that it will be useful,
8  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
9  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10  *  GNU General Public License for more details.
11  *
12  *  Copyright (C) 2004 IDT Inc.
13  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
14  */
15 #ifndef __ASM_RC32434_RB_H
16 #define __ASM_RC32434_RB_H
17 
18 #include <linux/genhd.h>
19 
20 #define REGBASE		0x18000000
21 #define IDT434_REG_BASE	((volatile void *) KSEG1ADDR(REGBASE))
22 #define UART0BASE	0x58000
23 #define RST		(1 << 15)
24 #define DEV0BASE	0x010000
25 #define DEV0MASK	0x010004
26 #define DEV0C		0x010008
27 #define DEV0T		0x01000C
28 #define DEV1BASE	0x010010
29 #define DEV1MASK	0x010014
30 #define DEV1C		0x010018
31 #define DEV1TC		0x01001C
32 #define DEV2BASE	0x010020
33 #define DEV2MASK	0x010024
34 #define DEV2C		0x010028
35 #define DEV2TC		0x01002C
36 #define DEV3BASE	0x010030
37 #define DEV3MASK	0x010034
38 #define DEV3C		0x010038
39 #define DEV3TC		0x01003C
40 #define BTCS		0x010040
41 #define BTCOMPARE	0x010044
42 #define GPIOBASE	0x050000
43 /* Offsets relative to GPIOBASE */
44 #define GPIOFUNC	0x00
45 #define GPIOCFG		0x04
46 #define GPIOD		0x08
47 #define GPIOILEVEL	0x0C
48 #define GPIOISTAT	0x10
49 #define GPIONMIEN	0x14
50 #define IMASK6		0x38
51 #define LO_WPX		(1 << 0)
52 #define LO_ALE		(1 << 1)
53 #define LO_CLE		(1 << 2)
54 #define LO_CEX		(1 << 3)
55 #define LO_FOFF		(1 << 5)
56 #define LO_SPICS	(1 << 6)
57 #define LO_ULED		(1 << 7)
58 
59 #define BIT_TO_MASK(x)	(1 << x)
60 
61 struct dev_reg {
62 	u32	base;
63 	u32	mask;
64 	u32	ctl;
65 	u32	timing;
66 };
67 
68 struct korina_device {
69 	char *name;
70 	unsigned char mac[6];
71 	struct net_device *dev;
72 };
73 
74 struct cf_device {
75 	int gpio_pin;
76 	void *dev;
77 	struct gendisk *gd;
78 };
79 
80 struct mpmc_device {
81 	unsigned char	state;
82 	spinlock_t	lock;
83 	void __iomem 	*base;
84 };
85 
86 extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
87 extern unsigned char get_latch_u5(void);
88 
89 #endif  /* __ASM_RC32434_RB_H */
90