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Searched refs:MCFINT_VECBASE (Results 1 – 11 of 11) sorted by relevance

/arch/m68k/include/asm/
Dm54xxsim.h14 #define MCFINT_VECBASE 64 macro
42 #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
43 #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
44 #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
45 #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
46 #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
47 #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
Dm520xsim.h46 #define MCFINT_VECBASE 64 macro
56 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
57 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
58 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
60 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
61 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
62 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
64 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
135 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
Dm523xsim.h36 #define MCFINT_VECBASE 64 /* Vector base number */ macro
46 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
50 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
54 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
186 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
Dm527xsim.h36 #define MCFINT_VECBASE 64 /* Vector base number */ macro
51 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
52 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
53 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
55 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
56 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
57 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
62 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
194 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
289 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
Dm528xsim.h36 #define MCFINT_VECBASE 64 /* Vector base number */ macro
46 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
50 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
54 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
252 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
Dm5272sim.h97 #define MCFINT_VECBASE 64 /* Base of interrupts */ macro
Dm532xsim.h22 #define MCFINT_VECBASE 64 macro
31 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
32 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
33 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
35 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
36 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
37 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
39 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
1199 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/arch/m68k/platform/5272/
Dintc.c44 static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
85 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { in intc_irq_mask()
87 irq -= MCFINT_VECBASE; in intc_irq_mask()
97 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { in intc_irq_unmask()
99 irq -= MCFINT_VECBASE; in intc_irq_unmask()
110 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { in intc_irq_ack()
111 irq -= MCFINT_VECBASE; in intc_irq_ack()
126 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { in intc_irq_set_type()
127 irq -= MCFINT_VECBASE; in intc_irq_set_type()
174 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) in init_IRQ()
[all …]
/arch/m68k/platform/coldfire/
Dintc-simr.c69 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_mask()
79 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_unmask()
111 irq -= MCFINT_VECBASE; in intc_irq_startup()
179 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); in init_IRQ()
180 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { in init_IRQ()
Dintc-2.c52 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_mask()
70 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_unmask()
114 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_startup()
203 for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { in init_IRQ()
Dpit.c96 .irq = MCFINT_VECBASE + MCFINT_PIT1,
162 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); in hw_timer_init()