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Searched refs:MDREFR (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-pxa/
Dh5000.c181 __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR); in fix_msc()
Dsleep.S55 ldr r4, =MDREFR
96 ldr r4, =MDREFR
Dcpufreq-pxa2xx.c336 preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR); in pxa_set_target()
375 : "r" (MDREFR), "r" (cclkcfg), in pxa_set_target()
Dpxa27x.c271 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); in pxa27x_cpu_pm_save()
279 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); in pxa27x_cpu_pm_restore()
/arch/arm/mach-sa1100/
Dsleep.S36 ldr r6, =MDREFR
124 @ Step 2 clear DRI field in MDREFR
127 @ Step 3 set SLFRSH bit in MDREFR
Dcpu-sa1110.c181 sd->mdrefr = MDREFR & 0xffbffff0; in sdram_calculate_timing()
203 MDREFR = (MDREFR & 0xffff000f) | (dri << 4); in sdram_set_refresh()
204 (void) MDREFR; in sdram_set_refresh()
/arch/arm/mach-pxa/include/mach/
Dsmemc.h19 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ macro
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h1574 #define MDREFR __REG(0xA000001C) macro