1 #ifndef __MACH_MX51_H__ 2 #define __MACH_MX51_H__ 3 4 /* 5 * IROM 6 */ 7 #define MX51_IROM_BASE_ADDR 0x0 8 #define MX51_IROM_SIZE SZ_64K 9 10 /* 11 * IRAM 12 */ 13 #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ 14 #define MX51_IRAM_PARTITIONS 16 15 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 16 17 #define MX51_GPU_BASE_ADDR 0x20000000 18 #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 19 #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 20 21 /* 22 * SPBA global module enabled #0 23 */ 24 #define MX51_SPBA0_BASE_ADDR 0x70000000 25 #define MX51_SPBA0_SIZE SZ_1M 26 27 #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) 28 #define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) 29 #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) 30 #define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) 31 #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) 32 #define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) 33 #define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) 34 #define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) 35 #define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) 36 #define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) 37 #define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) 38 #define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) 39 40 /* 41 * AIPS 1 42 */ 43 #define MX51_AIPS1_BASE_ADDR 0x73f00000 44 #define MX51_AIPS1_SIZE SZ_1M 45 46 #define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) 47 #define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000) 48 #define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200) 49 #define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400) 50 #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) 51 #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) 52 #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) 53 #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) 54 #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) 55 #define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) 56 #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) 57 #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) 58 #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) 59 #define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) 60 #define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) 61 #define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) 62 #define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) 63 #define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) 64 #define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) 65 #define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) 66 #define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) 67 #define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) 68 #define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) 69 70 /* 71 * AIPS 2 72 */ 73 #define MX51_AIPS2_BASE_ADDR 0x83f00000 74 #define MX51_AIPS2_SIZE SZ_1M 75 76 #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) 77 #define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) 78 #define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) 79 #define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) 80 #define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) 81 #define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) 82 #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) 83 #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) 84 #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) 85 #define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) 86 #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) 87 #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) 88 #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) 89 #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) 90 #define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) 91 #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) 92 #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) 93 #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) 94 #define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) 95 #define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) 96 #define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) 97 #define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) 98 #define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) 99 #define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) 100 #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) 101 #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) 102 #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) 103 #define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) 104 #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) 105 #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) 106 #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) 107 #define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) 108 109 #define MX51_CSD0_BASE_ADDR 0x90000000 110 #define MX51_CSD1_BASE_ADDR 0xa0000000 111 #define MX51_CS0_BASE_ADDR 0xb0000000 112 #define MX51_CS1_BASE_ADDR 0xb8000000 113 #define MX51_CS2_BASE_ADDR 0xc0000000 114 #define MX51_CS3_BASE_ADDR 0xc8000000 115 #define MX51_CS4_BASE_ADDR 0xcc000000 116 #define MX51_CS5_BASE_ADDR 0xce000000 117 118 /* 119 * NFC 120 */ 121 #define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ 122 #define MX51_NFC_AXI_SIZE SZ_64K 123 124 #define MX51_GPU2D_BASE_ADDR 0xd0000000 125 #define MX51_TZIC_BASE_ADDR 0xe0000000 126 #define MX51_TZIC_SIZE SZ_16K 127 128 #define MX51_IO_P2V(x) IMX_IO_P2V(x) 129 #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) 130 131 /* 132 * defines for SPBA modules 133 */ 134 #define MX51_SPBA_SDHC1 0x04 135 #define MX51_SPBA_SDHC2 0x08 136 #define MX51_SPBA_UART3 0x0c 137 #define MX51_SPBA_CSPI1 0x10 138 #define MX51_SPBA_SSI2 0x14 139 #define MX51_SPBA_SDHC3 0x20 140 #define MX51_SPBA_SDHC4 0x24 141 #define MX51_SPBA_SPDIF 0x28 142 #define MX51_SPBA_ATA 0x30 143 #define MX51_SPBA_SLIM 0x34 144 #define MX51_SPBA_HSI2C 0x38 145 #define MX51_SPBA_CTRL 0x3c 146 147 /* 148 * Defines for modules using static and dynamic DMA channels 149 */ 150 #define MX51_MXC_DMA_CHANNEL_IRAM 30 151 #define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL 152 #define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL 153 #define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL 154 #define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL 155 #define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL 156 #define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL 157 #define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL 158 #define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL 159 #define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL 160 #define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL 161 #define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL 162 #define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL 163 #ifdef CONFIG_SDMA_IRAM 164 #define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) 165 #else /*CONFIG_SDMA_IRAM */ 166 #define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL 167 #endif /*CONFIG_SDMA_IRAM */ 168 #define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL 169 #define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL 170 #define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL 171 #define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL 172 #define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL 173 #define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL 174 #define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL 175 #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL 176 #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL 177 178 #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 179 180 /* 181 * DMA request assignments 182 */ 183 #define MX51_DMA_REQ_VPU 0 184 #define MX51_DMA_REQ_GPC 1 185 #define MX51_DMA_REQ_ATA_RX 2 186 #define MX51_DMA_REQ_ATA_TX 3 187 #define MX51_DMA_REQ_ATA_TX_END 4 188 #define MX51_DMA_REQ_SLIM_B 5 189 #define MX51_DMA_REQ_CSPI1_RX 6 190 #define MX51_DMA_REQ_CSPI1_TX 7 191 #define MX51_DMA_REQ_CSPI2_RX 8 192 #define MX51_DMA_REQ_CSPI2_TX 9 193 #define MX51_DMA_REQ_HS_I2C_TX 10 194 #define MX51_DMA_REQ_HS_I2C_RX 11 195 #define MX51_DMA_REQ_FIRI_RX 12 196 #define MX51_DMA_REQ_FIRI_TX 13 197 #define MX51_DMA_REQ_EXTREQ1 14 198 #define MX51_DMA_REQ_GPU 15 199 #define MX51_DMA_REQ_UART2_RX 16 200 #define MX51_DMA_REQ_UART2_TX 17 201 #define MX51_DMA_REQ_UART1_RX 18 202 #define MX51_DMA_REQ_UART1_TX 19 203 #define MX51_DMA_REQ_SDHC1 20 204 #define MX51_DMA_REQ_SDHC2 21 205 #define MX51_DMA_REQ_SSI2_RX1 22 206 #define MX51_DMA_REQ_SSI2_TX1 23 207 #define MX51_DMA_REQ_SSI2_RX0 24 208 #define MX51_DMA_REQ_SSI2_TX0 25 209 #define MX51_DMA_REQ_SSI1_RX1 26 210 #define MX51_DMA_REQ_SSI1_TX1 27 211 #define MX51_DMA_REQ_SSI1_RX0 28 212 #define MX51_DMA_REQ_SSI1_TX0 29 213 #define MX51_DMA_REQ_EMI_RD 30 214 #define MX51_DMA_REQ_CTI2_0 31 215 #define MX51_DMA_REQ_EMI_WR 32 216 #define MX51_DMA_REQ_CTI2_1 33 217 #define MX51_DMA_REQ_EPIT2 34 218 #define MX51_DMA_REQ_SSI3_RX1 35 219 #define MX51_DMA_REQ_IPU 36 220 #define MX51_DMA_REQ_SSI3_TX1 37 221 #define MX51_DMA_REQ_CSPI_RX 38 222 #define MX51_DMA_REQ_CSPI_TX 39 223 #define MX51_DMA_REQ_SDHC3 40 224 #define MX51_DMA_REQ_SDHC4 41 225 #define MX51_DMA_REQ_SLIM_B_TX 42 226 #define MX51_DMA_REQ_UART3_RX 43 227 #define MX51_DMA_REQ_UART3_TX 44 228 #define MX51_DMA_REQ_SPDIF 45 229 #define MX51_DMA_REQ_SSI3_RX0 46 230 #define MX51_DMA_REQ_SSI3_TX0 47 231 232 /* 233 * Interrupt numbers 234 */ 235 #define MX51_INT_BASE 0 236 #define MX51_INT_RESV0 0 237 #define MX51_INT_ESDHC1 1 238 #define MX51_INT_ESDHC2 2 239 #define MX51_INT_ESDHC3 3 240 #define MX51_INT_ESDHC4 4 241 #define MX51_INT_RESV5 5 242 #define MX51_INT_SDMA 6 243 #define MX51_INT_IOMUX 7 244 #define MX51_INT_NFC 8 245 #define MX51_INT_VPU 9 246 #define MX51_INT_IPU_ERR 10 247 #define MX51_INT_IPU_SYN 11 248 #define MX51_INT_GPU 12 249 #define MX51_INT_RESV13 13 250 #define MX51_INT_USB_HS1 14 251 #define MX51_INT_EMI 15 252 #define MX51_INT_USB_HS2 16 253 #define MX51_INT_USB_HS3 17 254 #define MX51_INT_USB_OTG 18 255 #define MX51_INT_SAHARA_H0 19 256 #define MX51_INT_SAHARA_H1 20 257 #define MX51_INT_SCC_SMN 21 258 #define MX51_INT_SCC_STZ 22 259 #define MX51_INT_SCC_SCM 23 260 #define MX51_INT_SRTC_NTZ 24 261 #define MX51_INT_SRTC_TZ 25 262 #define MX51_INT_RTIC 26 263 #define MX51_INT_CSU 27 264 #define MX51_INT_SLIM_B 28 265 #define MX51_INT_SSI1 29 266 #define MX51_INT_SSI2 30 267 #define MX51_INT_UART1 31 268 #define MX51_INT_UART2 32 269 #define MX51_INT_UART3 33 270 #define MX51_INT_RESV34 34 271 #define MX51_INT_RESV35 35 272 #define MX51_INT_ECSPI1 36 273 #define MX51_INT_ECSPI2 37 274 #define MX51_INT_CSPI 38 275 #define MX51_INT_GPT 39 276 #define MX51_INT_EPIT1 40 277 #define MX51_INT_EPIT2 41 278 #define MX51_INT_GPIO1_INT7 42 279 #define MX51_INT_GPIO1_INT6 43 280 #define MX51_INT_GPIO1_INT5 44 281 #define MX51_INT_GPIO1_INT4 45 282 #define MX51_INT_GPIO1_INT3 46 283 #define MX51_INT_GPIO1_INT2 47 284 #define MX51_INT_GPIO1_INT1 48 285 #define MX51_INT_GPIO1_INT0 49 286 #define MX51_INT_GPIO1_LOW 50 287 #define MX51_INT_GPIO1_HIGH 51 288 #define MX51_INT_GPIO2_LOW 52 289 #define MX51_INT_GPIO2_HIGH 53 290 #define MX51_INT_GPIO3_LOW 54 291 #define MX51_INT_GPIO3_HIGH 55 292 #define MX51_INT_GPIO4_LOW 56 293 #define MX51_INT_GPIO4_HIGH 57 294 #define MX51_INT_WDOG1 58 295 #define MX51_INT_WDOG2 59 296 #define MX51_INT_KPP 60 297 #define MX51_INT_PWM1 61 298 #define MX51_INT_I2C1 62 299 #define MX51_INT_I2C2 63 300 #define MX51_INT_HS_I2C 64 301 #define MX51_INT_RESV65 65 302 #define MX51_INT_RESV66 66 303 #define MX51_INT_SIM_IPB 67 304 #define MX51_INT_SIM_DAT 68 305 #define MX51_INT_IIM 69 306 #define MX51_INT_ATA 70 307 #define MX51_INT_CCM1 71 308 #define MX51_INT_CCM2 72 309 #define MX51_INT_GPC1 73 310 #define MX51_INT_GPC2 74 311 #define MX51_INT_SRC 75 312 #define MX51_INT_NM 76 313 #define MX51_INT_PMU 77 314 #define MX51_INT_CTI_IRQ 78 315 #define MX51_INT_CTI1_TG0 79 316 #define MX51_INT_CTI1_TG1 80 317 #define MX51_INT_MCG_ERR 81 318 #define MX51_INT_MCG_TMR 82 319 #define MX51_INT_MCG_FUNC 83 320 #define MX51_INT_GPU2_IRQ 84 321 #define MX51_INT_GPU2_BUSY 85 322 #define MX51_INT_RESV86 86 323 #define MX51_INT_FEC 87 324 #define MX51_INT_OWIRE 88 325 #define MX51_INT_CTI1_TG2 89 326 #define MX51_INT_SJC 90 327 #define MX51_INT_SPDIF 91 328 #define MX51_INT_TVE 92 329 #define MX51_INT_FIRI 93 330 #define MX51_INT_PWM2 94 331 #define MX51_INT_SLIM_EXP 95 332 #define MX51_INT_SSI3 96 333 #define MX51_INT_EMI_BOOT 97 334 #define MX51_INT_CTI1_TG3 98 335 #define MX51_INT_SMC_RX 99 336 #define MX51_INT_VPU_IDLE 100 337 #define MX51_INT_EMI_NFC 101 338 #define MX51_INT_GPU_IDLE 102 339 340 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 341 extern int mx51_revision(void); 342 extern void mx51_display_revision(void); 343 #endif 344 345 #endif /* ifndef __MACH_MX51_H__ */ 346