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Searched refs:NR_CPUS (Results 1 – 25 of 230) sorted by relevance

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/arch/powerpc/include/asm/
Dirq.h56 extern struct thread_info *critirq_ctx[NR_CPUS];
57 extern struct thread_info *dbgirq_ctx[NR_CPUS];
58 extern struct thread_info *mcheckirq_ctx[NR_CPUS];
67 extern struct thread_info *hardirq_ctx[NR_CPUS];
68 extern struct thread_info *softirq_ctx[NR_CPUS];
Dcputhreads.h46 for (i = 0; i < NR_CPUS; i += threads_per_core) { in cpu_thread_mask_to_cores()
56 return NR_CPUS >> threads_shift; in cpu_nr_cores()
/arch/mips/kernel/
Dsmtc-proc.c29 unsigned long selfipis[NR_CPUS];
31 struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS];
57 for (i=0; i < NR_CPUS; i++) { in proc_read_smtc()
65 for(i = 0; i < NR_CPUS; i++) { in proc_read_smtc()
82 for (i=0; i<NR_CPUS; i++) { in init_smtc_stats()
Dsmtc.c85 struct smtc_ipi_q IPIQ[NR_CPUS];
183 int tcnoprog[NR_CPUS];
185 static int clock_hang_reported[NR_CPUS];
307 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) { in smtc_build_cpu_map()
369 int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu; in smtc_prepare_cpus()
387 for (i=0; i<NR_CPUS; i++) { in smtc_prepare_cpus()
427 if (ntc > NR_CPUS) in smtc_prepare_cpus()
428 ntc = NR_CPUS; in smtc_prepare_cpus()
555 nipi = NR_CPUS * IPIBUF_PER_CPU; in smtc_prepare_cpus()
588 extern u32 kernelsp[NR_CPUS]; in smtc_boot_secondary()
[all …]
/arch/s390/include/asm/
Dtopology.h11 extern unsigned char cpu_core_id[NR_CPUS];
12 extern cpumask_t cpu_core_map[NR_CPUS];
23 extern unsigned char cpu_book_id[NR_CPUS];
24 extern cpumask_t cpu_book_map[NR_CPUS];
/arch/blackfin/kernel/cplb-nompu/
Dcplbmgr.c29 int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
30 int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
31 int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
68 static int icplb_rr_index[NR_CPUS] PDT_ATTR;
69 static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
/arch/blackfin/include/asm/
Dsmp.h24 extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
33 extern unsigned long icache_invld_count[NR_CPUS];
36 extern unsigned long dcache_invld_count[NR_CPUS];
Dcplbinit.h35 extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
36 extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
50 extern unsigned long *current_rwx_mask[NR_CPUS];
/arch/arm/mach-highbank/
Dplatsmp.c50 if (ncores > NR_CPUS) { in smp_init_cpus()
54 ncores, NR_CPUS); in smp_init_cpus()
55 ncores = NR_CPUS; in smp_init_cpus()
/arch/ia64/include/asm/native/
Dirq.h27 #if (NR_VECTORS + 32 * NR_CPUS) < 1024
28 #define IA64_NATIVE_NR_IRQS (NR_VECTORS + 32 * NR_CPUS)
/arch/x86/include/asm/
Dirq_vectors.h123 #if NR_CPUS <= 32
124 # define NUM_INVALIDATE_TLB_VECTORS (NR_CPUS)
163 # define CPU_VECTOR_LIMIT (64 * NR_CPUS)
/arch/ia64/kernel/
Derr_inject.c43 static u64 call_start[NR_CPUS];
44 static u64 phys_addr[NR_CPUS];
45 static u64 err_type_info[NR_CPUS];
46 static u64 err_struct_info[NR_CPUS];
51 } __attribute__((__aligned__(16))) err_data_buffer[NR_CPUS];
52 static s64 status[NR_CPUS];
53 static u64 capabilities[NR_CPUS];
54 static u64 resources[NR_CPUS];
/arch/mips/include/asm/
Dsmtc.h26 #if NR_CPUS <= 8
29 #if NR_CPUS <= 16
Dfixmap.h52 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
59 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
Dsmp.h30 extern int __cpu_number_map[NR_CPUS];
34 extern int __cpu_logical_map[NR_CPUS];
/arch/ia64/include/asm/
Dsmp.h55 int cpu_phys_id[NR_CPUS];
60 extern cpumask_t cpu_core_map[NR_CPUS];
80 for (i = 0; i < NR_CPUS; ++i) in cpu_logical_id()
Dnuma.h25 extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
51 extern struct node_cpuid_s node_cpuid[NR_CPUS];
/arch/mn10300/mm/
Dmmu-context.c20 unsigned long mmu_context_cache[NR_CPUS] = {
21 [0 ... NR_CPUS - 1] =
/arch/sh/include/asm/
Dsmp.h18 extern int __cpu_number_map[NR_CPUS];
22 extern int __cpu_logical_map[NR_CPUS];
/arch/blackfin/kernel/cplb-mpu/
Dcplbmgr.c28 unsigned long *current_rwx_mask[NR_CPUS];
30 int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
31 int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
32 int nr_cplb_flush[NR_CPUS];
63 static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
/arch/m32r/kernel/
Dsmpboot.c83 struct cpuinfo_m32r cpu_data[NR_CPUS] __cacheline_aligned;
94 static volatile int physid_2_cpu[NR_CPUS];
98 volatile int cpu_2_physid[NR_CPUS];
173 if (nr_cpu > NR_CPUS) { in smp_prepare_cpus()
175 nr_cpu, NR_CPUS); in smp_prepare_cpus()
206 for (phys_id = 0 ; phys_id < NR_CPUS ; phys_id++) { in smp_prepare_cpus()
606 for (i = 0 ; i < NR_CPUS ; i++) { in init_cpu_to_physid()
/arch/powerpc/lib/
Dlocks.c34 BUG_ON(holder_cpu >= NR_CPUS); in __spin_yield()
59 BUG_ON(holder_cpu >= NR_CPUS); in __rw_yield()
/arch/m32r/mm/
Dfault-nommu.c39 unsigned int tlb_entry_i_dat[NR_CPUS];
40 unsigned int tlb_entry_d_dat[NR_CPUS];
/arch/ia64/mm/
Dnuma.c30 struct node_cpuid_s node_cpuid[NR_CPUS] =
31 { [0 ... NR_CPUS-1] = { .phys_id = 0, .nid = NUMA_NO_NODE } };
/arch/sparc/include/asm/
Dirq_64.h95 extern void *hardirq_stack[NR_CPUS];
96 extern void *softirq_stack[NR_CPUS];

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