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Searched refs:NULL (Results 1 – 25 of 2170) sorted by relevance

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/arch/arm/mach-omap2/
Dmux2420.c46 NULL, NULL, "etk_d2", NULL),
49 NULL, NULL, "etk_d3", NULL),
52 NULL, NULL, "etk_d4", NULL),
55 NULL, NULL, "etk_d5", NULL),
58 NULL, NULL, "etk_d6", NULL),
61 NULL, NULL, "etk_d7", NULL),
63 "cam_d6", "hw_dbg8", NULL, NULL,
64 NULL, NULL, "etk_d8", NULL),
66 "cam_d7", "hw_dbg9", NULL, NULL,
67 NULL, NULL, "etk_d9", NULL),
[all …]
Dmux2430.c46 NULL, NULL, "etk_d2", "safe_mode"),
48 "cam_d10", NULL, NULL, "gpio_146",
49 NULL, NULL, "etk_d12", "safe_mode"),
51 "cam_d11", NULL, NULL, "gpio_145",
52 NULL, NULL, "etk_d13", "safe_mode"),
55 NULL, NULL, "etk_d3", "safe_mode"),
58 NULL, NULL, "etk_d4", "safe_mode"),
61 NULL, NULL, "etk_d5", "safe_mode"),
64 NULL, NULL, "etk_d6", "safe_mode"),
67 NULL, NULL, "etk_d7", "safe_mode"),
[all …]
Dmux34xx.c45 "cam_d0", NULL, NULL, NULL,
46 "gpio_99", NULL, NULL, "safe_mode"),
48 "cam_d1", NULL, NULL, NULL,
49 "gpio_100", NULL, NULL, "safe_mode"),
51 "cam_d10", NULL, NULL, NULL,
52 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
54 "cam_d11", NULL, NULL, NULL,
55 "gpio_110", "hw_dbg9", NULL, "safe_mode"),
57 "cam_d2", NULL, NULL, NULL,
58 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
[all …]
Dmux44xx.c54 _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
55 NULL, NULL, NULL, NULL),
56 _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
57 NULL, NULL, NULL, NULL),
58 _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
59 NULL, NULL, NULL, NULL),
60 _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
61 NULL, NULL, NULL, NULL),
63 "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
65 "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
[all …]
/arch/ia64/kernel/
Dperfmon_montecito.h16 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
17 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
18 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
19 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
20 /* pmc4 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(4),0, 0, …
21 /* pmc5 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(5),0, 0, …
22 /* pmc6 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(6),0, 0, …
23 /* pmc7 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(7),0, 0, …
24 /* pmc8 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(8),0, 0, …
25 /* pmc9 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(9),0, 0, …
[all …]
Dperfmon_generic.h10 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
11 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
15 /* pmc5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
16 /* pmc6 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
17 /* pmc7 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
18 { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
22 /* pmd0 */ { PFM_REG_NOTIMPL , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}},
[all …]
Dpalinfo.c474 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
475 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
476 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
477 NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,
490 NULL, NULL, NULL, NULL,
510 NULL,
514 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
518 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
519 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
520 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
[all …]
Dperfmon_itanium.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 /* pmc4 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
16 /* pmc5 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
17 /* pmc6 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
18 /* pmc7 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL,…
19 /* pmc8 */ { PFM_REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0U…
20 /* pmc9 */ { PFM_REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0U…
[all …]
Dperfmon_mckinley.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
13 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
14 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL…
15 /* pmc4 */ { PFM_REG_COUNTING, 6, 0x0000000000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDE…
16 /* pmc5 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(5),0UL, 0UL,…
17 /* pmc6 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(6),0UL, 0UL,…
18 /* pmc7 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(7),0UL, 0UL,…
19 /* pmc8 */ { PFM_REG_CONFIG , 0, 0xffffffff3fffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_ch…
20 /* pmc9 */ { PFM_REG_CONFIG , 0, 0xffffffff3ffffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_ch…
[all …]
/arch/sh/boards/
Dboard-sh7757lcr.c332 gpio_request(GPIO_FN_ET0_MDC, NULL); in sh7757lcr_devices_setup()
333 gpio_request(GPIO_FN_ET0_MDIO, NULL); in sh7757lcr_devices_setup()
334 gpio_request(GPIO_FN_ET1_MDC, NULL); in sh7757lcr_devices_setup()
335 gpio_request(GPIO_FN_ET1_MDIO, NULL); in sh7757lcr_devices_setup()
338 gpio_request(GPIO_FN_ON_NRE, NULL); in sh7757lcr_devices_setup()
339 gpio_request(GPIO_FN_ON_NWE, NULL); in sh7757lcr_devices_setup()
340 gpio_request(GPIO_FN_ON_NWP, NULL); in sh7757lcr_devices_setup()
341 gpio_request(GPIO_FN_ON_NCE0, NULL); in sh7757lcr_devices_setup()
342 gpio_request(GPIO_FN_ON_R_B0, NULL); in sh7757lcr_devices_setup()
343 gpio_request(GPIO_FN_ON_ALE, NULL); in sh7757lcr_devices_setup()
[all …]
/arch/arm/mach-imx/
Dclock-imx25.c83 return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1); in get_rate_ahb()
88 return get_rate_ahb(NULL) >> 1; in get_rate_ipg()
101 fref = get_rate_ahb(NULL); in get_rate_per()
218 DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
219 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
220 DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
221 DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
222 DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
223 DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
224 DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
[all …]
Dclock-imx27.c534 DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk);
535 DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk);
536 DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk);
537 DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk);
538 DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk);
539 DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk);
540 DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk);
541 DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk);
542 DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk);
543 DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk);
[all …]
Dclock-imx35.c159 return get_rate_ahb(NULL) >> 1; in get_rate_ipg()
278 return get_rate_ahb(NULL) / (div + 1); in get_rate_ipg_per()
340 DEFINE_CLOCK(asrc_clk, 0, MX35_CCM_CGR0, 0, NULL, NULL);
341 DEFINE_CLOCK(pata_clk, 0, MX35_CCM_CGR0, 2, get_rate_ipg, NULL);
343 DEFINE_CLOCK(can1_clk, 0, MX35_CCM_CGR0, 6, get_rate_ipg, NULL);
344 DEFINE_CLOCK(can2_clk, 1, MX35_CCM_CGR0, 8, get_rate_ipg, NULL);
345 DEFINE_CLOCK(cspi1_clk, 0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
346 DEFINE_CLOCK(cspi2_clk, 1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
347 DEFINE_CLOCK(ect_clk, 0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
348 DEFINE_CLOCK(edio_clk, 0, MX35_CCM_CGR0, 16, NULL, NULL);
[all …]
Dclock-imx31.c470 DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
471 DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
473 DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
474 DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
475 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
476 DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
477 DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
478 DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
479 DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
480 DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
[all …]
Dimx53-dt.c30 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
31 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
32 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
33 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
34 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
35 OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
36 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
37 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
38 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
39 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
[all …]
/arch/arm/mach-msm/
Ddevices-msm7x30.c134 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
135 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
136 CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0),
137 CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF),
138 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
139 CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0),
140 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
141 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
142 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
143 CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF),
[all …]
/arch/parisc/hpux/
Dsys_hpux.c430 char *fsname = NULL; in hpux_sysfs()
509 NULL,
529 NULL,
530 NULL,
531 NULL, /* 50 */
534 NULL,
545 NULL,
546 NULL, /* 65 */
548 NULL,
549 NULL,
[all …]
/arch/mips/bcm47xx/
Dsprom.c86 create_key(prefix, NULL, name, key, sizeof(key)); in NVRAM_READ_VAL()
109 create_key(prefix, NULL, name, key, sizeof(key)); in nvram_read_leddc()
135 create_key(prefix, NULL, name, key, sizeof(key)); in nvram_read_macaddr()
150 create_key(prefix, NULL, name, key, sizeof(key)); in nvram_read_alpha2()
167 nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0); in bcm47xx_fill_sprom_r1234589()
168 nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0); in bcm47xx_fill_sprom_r1234589()
169 nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff); in bcm47xx_fill_sprom_r1234589()
170 nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff); in bcm47xx_fill_sprom_r1234589()
171 nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff); in bcm47xx_fill_sprom_r1234589()
172 nvram_read_u8(prefix, NULL, "ledbh3", &sprom->gpio3, 0xff); in bcm47xx_fill_sprom_r1234589()
[all …]
/arch/sh/boards/mach-se/7724/
Dsetup.c410 .dma_mask = NULL, /* not use dma */
439 .dma_mask = NULL, /* not use dma */
703 gpio_request(GPIO_FN_STATUS2, NULL); in devices_setup()
706 gpio_request(GPIO_FN_STATUS0, NULL); in devices_setup()
709 gpio_request(GPIO_FN_PDSTATUS, NULL); in devices_setup()
718 gpio_request(GPIO_FN_INTC_IRQ0, NULL); in devices_setup()
719 gpio_request(GPIO_FN_INTC_IRQ1, NULL); in devices_setup()
720 gpio_request(GPIO_FN_INTC_IRQ2, NULL); in devices_setup()
723 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); in devices_setup()
724 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); in devices_setup()
[all …]
/arch/arm/mach-shmobile/
Dboard-kota2.c417 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); in kota2_init()
418 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); in kota2_init()
419 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); in kota2_init()
420 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); in kota2_init()
423 gpio_request(GPIO_FN_SCIFA4_TXD, NULL); in kota2_init()
424 gpio_request(GPIO_FN_SCIFA4_RXD, NULL); in kota2_init()
425 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); in kota2_init()
426 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); in kota2_init()
429 gpio_request(GPIO_FN_D0_NAF0, NULL); in kota2_init()
430 gpio_request(GPIO_FN_D1_NAF1, NULL); in kota2_init()
[all …]
Dboard-g3evm.c135 .dma_mask = NULL,
253 gpio_request(GPIO_PORT22, NULL); in g3evm_init()
258 gpio_request(GPIO_PORT23, NULL); in g3evm_init()
263 gpio_request(GPIO_PORT24, NULL); in g3evm_init()
268 gpio_request(GPIO_FN_SCIFA1_TXD, NULL); in g3evm_init()
269 gpio_request(GPIO_FN_SCIFA1_RXD, NULL); in g3evm_init()
270 gpio_request(GPIO_FN_SCIFA1_CTS, NULL); in g3evm_init()
271 gpio_request(GPIO_FN_SCIFA1_RTS, NULL); in g3evm_init()
274 gpio_request(GPIO_FN_VBUS0, NULL); in g3evm_init()
275 gpio_request(GPIO_FN_PWEN, NULL); in g3evm_init()
[all …]
/arch/sh/boards/mach-ecovec24/
Dsetup.c191 .dma_mask = NULL, /* not use dma */
227 .dma_mask = NULL, /* not use dma */
274 .dma_mask = NULL, /* not use dma */
487 gpio_request(GPIO_PTZ0, NULL); in ts_get_pendown_state()
493 gpio_request(GPIO_FN_INTC_IRQ0, NULL); in ts_get_pendown_state()
500 gpio_request(GPIO_FN_INTC_IRQ0, NULL); in ts_init()
1029 gpio_request(GPIO_FN_STATUS0, NULL); in arch_setup()
1030 gpio_request(GPIO_FN_STATUS2, NULL); in arch_setup()
1031 gpio_request(GPIO_FN_PDSTATUS, NULL); in arch_setup()
1034 gpio_request(GPIO_FN_SCIF0_TXD, NULL); in arch_setup()
[all …]
/arch/sh/boards/mach-migor/
Dsetup.c190 .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
312 camera_clk = clk_get(NULL, "video_clk"); in camera_power_on()
502 gpio_request(GPIO_FN_STATUS0, NULL); in migor_devices_setup()
505 gpio_request(GPIO_FN_PDSTATUS, NULL); in migor_devices_setup()
508 gpio_request(GPIO_FN_IRQ0, NULL); in migor_devices_setup()
513 gpio_request(GPIO_FN_KEYOUT0, NULL); in migor_devices_setup()
514 gpio_request(GPIO_FN_KEYOUT1, NULL); in migor_devices_setup()
515 gpio_request(GPIO_FN_KEYOUT2, NULL); in migor_devices_setup()
516 gpio_request(GPIO_FN_KEYOUT3, NULL); in migor_devices_setup()
517 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); in migor_devices_setup()
[all …]
/arch/arm/mach-exynos/
Dmach-exynos4-dt.c41 "exynos4210-uart.0", NULL),
43 "exynos4210-uart.1", NULL),
45 "exynos4210-uart.2", NULL),
47 "exynos4210-uart.3", NULL),
49 "exynos4-sdhci.0", NULL),
51 "exynos4-sdhci.1", NULL),
53 "exynos4-sdhci.2", NULL),
55 "exynos4-sdhci.3", NULL),
57 "s3c2440-i2c.0", NULL),
58 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
[all …]
/arch/arm/mach-tegra/
Dboard-dt-tegra30.c45 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
46 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
47 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
48 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
49 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
50 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
51 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
52 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
60 { NULL, NULL, 0, 0},
[all …]

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