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Searched refs:PLLCTL (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-davinci/
Dpm.c46 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
48 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
53 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
55 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
70 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
72 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
75 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
77 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
83 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
85 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
[all …]
Dsleep.S90 ldr ip, [r3, #PLLCTL]
93 str ip, [r3, #PLLCTL]
101 ldr ip, [r3, #PLLCTL]
103 str ip, [r3, #PLLCTL]
121 ldr ip, [r3, #PLLCTL]
123 str ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
128 str ip, [r3, #PLLCTL]
135 ldr ip, [r3, #PLLCTL]
137 str ip, [r3, #PLLCTL]
[all …]
Dclock.c375 ctrl = __raw_readl(pll->base + PLLCTL); in clk_pllclk_recalc()
468 ctrl = __raw_readl(pll->base + PLLCTL); in davinci_set_pllrate()
472 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
478 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
492 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
498 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
Dclock.h20 #define PLLCTL 0x100 macro
Dtnetv107x.c680 tmp = __raw_readl(clk->pll_data->base + PLLCTL); in clk_sspll_recalc()
686 tmp = __raw_readl(clk->pll_data->base + PLLCTL); in clk_sspll_recalc()
/arch/c6x/include/asm/
Dclock.h25 #define PLLCTL 0x100 macro
/arch/c6x/platforms/
Dpll.c279 ctrl = pll_read(pll, PLLCTL); in clk_pllclk_recalc()