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Searched refs:PLLU (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-tegra/
Dclock.h43 #define PLLU (1 << 14) macro
Dtegra30_clocks.c166 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
914 if (c->flags & PLLU) in tegra30_pll_clk_init()
925 if (c->flags & PLLU) in tegra30_pll_clk_init()
1005 if (c->flags & PLLU) { in tegra30_pll_clk_set_rate()
1022 BUG_ON(c->flags & PLLU); in tegra30_pll_clk_set_rate()
1069 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); in tegra30_pll_clk_set_rate()
1085 if (c->flags & (PLLU | PLLD)) { in tegra30_pll_clk_set_rate()
2350 .flags = PLL_HAS_CPCON | PLLU,
Dtegra2_clocks.c633 if (c->flags & PLLU) in tegra2_pll_clk_init()
687 if (c->flags & PLLU) { in tegra2_pll_clk_set_rate()
1725 .flags = PLLU,