Searched refs:PLL_DIV (Results 1 – 17 of 17) sorted by relevance
67 #define PLL_DIV 0x00000002 macro205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
100 P0.H = hi(PLL_DIV);101 P0.L = lo(PLL_DIV);163 P0.H = hi(PLL_DIV);164 P0.L = lo(PLL_DIV);
18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
17 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
12 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
17 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
16 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)17 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
16 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
15 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
12 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
12 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
13 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
18 #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ macro
17 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
1329 D16(PLL_DIV); in bfin_debug_mmrs_init()