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Searched refs:PLL_MOD (Results 1 – 13 of 13) sorted by relevance

/arch/arm/mach-omap2/
Dclkt2xxx_apll.c52 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in omap2_clk_apll_enable()
59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); in omap2_clk_apll_enable()
106 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in omap2_clk_apll_disable()
108 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); in omap2_clk_apll_disable()
133 aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); in omap2xxx_get_apll_clkin()
Dclkt2xxx_dpllcore.c57 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); in omap2xxx_clk_get_core_rate()
76 core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); in omap2_dpllcore_round_rate()
114 mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); in omap2_reprogram_dpllcore()
139 tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); in omap2_reprogram_dpllcore()
Dcm2xxx_3xxx.c146 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_dpll_autoidle()
149 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_dpll_autoidle()
170 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_apll_autoidle()
173 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); in _omap2xxx_set_apll_autoidle()
333 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); in omap3_cm_save_context()
335 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); in omap3_cm_save_context()
337 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); in omap3_cm_save_context()
339 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); in omap3_cm_save_context()
341 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); in omap3_cm_save_context()
461 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, in omap3_cm_restore_context()
[all …]
Dpowerdomains3xxx_data.c239 .prcm_offs = PLL_MOD,
245 .prcm_offs = PLL_MOD,
251 .prcm_offs = PLL_MOD,
Dcontrol.c315 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); in omap3_save_scratchpad_contents()
322 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & in omap3_save_scratchpad_contents()
325 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); in omap3_save_scratchpad_contents()
327 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); in omap3_save_scratchpad_contents()
329 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); in omap3_save_scratchpad_contents()
Dclock3xxx_data.c409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
420 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
422 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
497 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
545 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
566 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
572 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
578 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
580 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
[all …]
Dsram242x.S132 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
227 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
321 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
323 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
325 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dsram243x.S132 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
227 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
321 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
323 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
325 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dprcm-common.h30 #define PLL_MOD 0x500 macro
42 #define OMAP3430_CCR_MOD PLL_MOD
Dclock2430_data.c108 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
113 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
141 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
152 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
184 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
221 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
251 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
2052 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); in omap2430_clk_init()
Dclock2420_data.c109 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
114 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
142 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
153 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
185 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
231 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
1953 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); in omap2420_clk_init()
Dsram34xx.S298 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
Dsleep34xx.S48 #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)