Home
last modified time | relevance | path

Searched refs:PMCR (Results 1 – 12 of 12) sorted by relevance

/arch/sh/kernel/cpu/sh4/
Dperf_event.c20 #define PMCR(n) (PM_CR_BASE + ((n) * 0x04)) macro
215 tmp = __raw_readw(PMCR(idx)); in sh7750_pmu_disable()
217 __raw_writew(tmp, PMCR(idx)); in sh7750_pmu_disable()
222 __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx)); in sh7750_pmu_enable()
223 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); in sh7750_pmu_enable()
231 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i)); in sh7750_pmu_disable_all()
239 __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i)); in sh7750_pmu_enable_all()
/arch/arm/mach-sa1100/
Dsleep.S110 ldr r12, =PMCR
139 @ Step 6 set force sleep bit in PMCR
Dsimpad.c246 PMCR = PMCR_SF; in simpad_power_off()
Dgeneric.c131 PMCR = PMCR_SF; in sa1100_power_off()
/arch/arm/mach-pxa/include/mach/
Dpxa3xx-regs.h29 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ macro
Dpxa2xx-regs.h23 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ macro
/arch/unicore32/kernel/
Dsleep.S103 @ prepare PMCR for PLL changing
/arch/arm/mach-pxa/
Dcm-x2xx.c404 PMCR = 0x00000005; in cmx2xx_suspend()
Dzeus.c896 PMCR = PSPR = 0; in zeus_map_io()
Dspitz.c947 PMCR = 0x00; in spitz_init()
Dtosa.c948 PMCR = 0x01; in tosa_init()
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h917 #define PMCR __REG(0x90020000) /* PM Control Reg. */ macro