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Searched refs:PTRS_PER_PTE (Results 1 – 25 of 84) sorted by relevance

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/arch/tile/include/asm/
Dpgtable_32.h36 #define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL)) macro
37 #define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
51 #define LAST_PKMAP PTRS_PER_PTE
Dpgtable_64.h43 #define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL)) macro
44 #define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
/arch/arm/include/asm/
Dpgtable-2level.h71 #define PTRS_PER_PTE 512 macro
75 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
77 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
Dpgtable-3level.h32 #define PTRS_PER_PTE 512 macro
36 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
38 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
Dhighmem.h7 #define LAST_PKMAP PTRS_PER_PTE
/arch/m68k/include/asm/
Dpgtable_mm.h56 #define PTRS_PER_PTE 16 macro
60 #define PTRS_PER_PTE 512 macro
64 #define PTRS_PER_PTE 1024 macro
/arch/mips/include/asm/
Dpgtable-64.h114 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) macro
131 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
150 extern pte_t invalid_pte_table[PTRS_PER_PTE];
151 extern pte_t empty_bad_page_table[PTRS_PER_PTE];
253 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
/arch/m68k/mm/
Dsun3mmu.c72 next_pgtable += PTRS_PER_PTE * sizeof (pte_t); in paging_init()
78 for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table) { in paging_init()
Dmcfmmu.c65 next_pgtable += PTRS_PER_PTE * sizeof(pte_t); in paging_init()
70 for (i = 0; i < PTRS_PER_PTE; ++i, ++pg_table) { in paging_init()
/arch/hexagon/include/asm/
Dpgtable.h99 #define PTRS_PER_PTE 1024 macro
103 #define PTRS_PER_PTE 256 macro
107 #define PTRS_PER_PTE 64 macro
111 #define PTRS_PER_PTE 16 macro
115 #define PTRS_PER_PTE 4 macro
453 #define __pte_offset(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
Dmem-layout.h89 #define LAST_PKMAP PTRS_PER_PTE
/arch/powerpc/mm/
Dsubpage-prot.c119 i = (addr >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); in subpage_prot_clear()
120 nw = PTRS_PER_PTE - i; in subpage_prot_clear()
197 i = (addr >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); in sys_subpage_prot()
198 nw = PTRS_PER_PTE - i; in sys_subpage_prot()
/arch/unicore32/include/asm/
Dpgalloc.h43 clean_dcache_area(pte, PTRS_PER_PTE * sizeof(pte_t)); in pte_alloc_one_kernel()
57 clean_dcache_area(page, PTRS_PER_PTE * sizeof(pte_t)); in pte_alloc_one()
/arch/x86/include/asm/
Dpgtable-2level_types.h35 #define PTRS_PER_PTE 1024 macro
Dpgtable-3level_types.h45 #define PTRS_PER_PTE 512 macro
Dpgtable_64_types.h45 #define PTRS_PER_PTE 512 macro
/arch/x86/power/
Dhibernate_32.c113 pfn += PTRS_PER_PTE; in resume_physical_mapping_init()
121 max_pte = pte + PTRS_PER_PTE; in resume_physical_mapping_init()
/arch/mn10300/mm/
Dinit.c61 for (loop = VMALLOC_START / (PAGE_SIZE * PTRS_PER_PTE); in paging_init()
62 loop < VMALLOC_END / (PAGE_SIZE * PTRS_PER_PTE); in paging_init()
/arch/powerpc/include/asm/
Dpgtable-ppc64-64k.h18 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) macro
Dpte-hash64-64k.h51 (pte_val(*((p) + PTRS_PER_PTE))) : 0 })
Dpgtable-ppc64-4k.h20 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) macro
/arch/parisc/kernel/
Dinit_task.c60 pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pte"), aligned(PAGE_S…
/arch/avr32/include/asm/
Dpgtable-2level.h19 #define PTRS_PER_PTE 1024 macro
/arch/um/include/asm/
Dpgtable-2level.h23 #define PTRS_PER_PTE 1024 macro
/arch/s390/include/asm/
Dpgtable.h104 #define PTRS_PER_PTE 256 macro
559 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) in pgste_get_lock()
560 : "Q" (ptep[PTRS_PER_PTE]) : "cc"); in pgste_get_lock()
571 : "=Q" (ptep[PTRS_PER_PTE]) in pgste_set_unlock()
572 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc"); in pgste_set_unlock()
1001 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE)); in ptep_modify_prot_commit()
1118 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))

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