Home
last modified time | relevance | path

Searched refs:R4600_V2_HIT_CACHEOP_WAR (Results 1 – 25 of 37) sorted by relevance

12

/arch/mips/include/asm/
Dwar.h127 #ifndef R4600_V2_HIT_CACHEOP_WAR
128 #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
/arch/mips/include/asm/mach-bcm63xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-wrppmc/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-lantiq/
Dwar.h12 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-cobalt/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ip27/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ip32/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-rc32434/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-bcm47xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-jz4740/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ar7/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ip22/
Dwar.h17 #define R4600_V2_HIT_CACHEOP_WAR 1 macro
/arch/mips/include/asm/mach-ip28/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-lasat/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-mipssim/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-rm/
Dwar.h17 #define R4600_V2_HIT_CACHEOP_WAR 1 macro
/arch/mips/include/asm/mach-tx39xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-yosemite/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-emma2rh/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-goldfish/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-powertv/
Dwar.h16 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-ath79/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-pnx8550/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-netlogic/
Dwar.h14 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/arch/mips/include/asm/mach-loongson/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro

12