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Searched refs:REG1 (Results 1 – 4 of 4) sorted by relevance

/arch/sparc/include/asm/
Dtsb.h98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \ argument
99 661: casa [TSB] ASI_N, REG1, REG2; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \ argument
106 661: casxa [TSB] ASI_N, REG1, REG2; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \ argument
120 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
122 andcc REG1, REG2, %g0; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
[all …]
Dtrap_block.h174 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ argument
175 lduh [THR + TI_CPU], REG1; \
177 sllx REG1, TRAP_BLOCK_SZ_SHIFT, REG1; \
179 add REG2, REG1, REG2; \
203 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) argument
/arch/m32r/kernel/
Dalign.c38 #define REG1(insn) (((insn) & 0x0f00) >> 8) macro
84 int dest = REG1(insn); in emu_addi()
98 set_reg(regs, REG1(insn), (int)imm); in emu_ldi()
105 int dest = REG1(insn); in emu_add()
118 int dest = REG1(insn); in emu_addx()
138 int dest = REG1(insn); in emu_and()
150 if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn))) in emu_cmp()
160 if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn))) in emu_cmpeq()
170 if ((unsigned int)get_reg(regs, REG1(insn)) in emu_cmpu()
194 set_reg(regs, REG1(insn), val); in emu_mv()
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/arch/sparc/kernel/
Dsys32.S15 #define SIGN1(STUB,SYSCALL,REG1) \ argument
20 sra REG1, 0, REG1
22 #define SIGN2(STUB,SYSCALL,REG1,REG2) \ argument
26 sra REG1, 0, REG1; \
30 #define SIGN3(STUB,SYSCALL,REG1,REG2,REG3) \ argument
33 STUB: sra REG1, 0, REG1; \
39 #define SIGN4(STUB,SYSCALL,REG1,REG2,REG3,REG4) \ argument
42 STUB: sra REG1, 0, REG1; \