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Searched refs:RS1 (Results 1 – 4 of 4) sorted by relevance

/arch/sparc/kernel/
Dvisemul.c135 #define RS1(INSN) (((INSN) >> 14) & 0x1f) macro
293 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in edge()
294 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); in edge()
371 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in array()
372 rs1 = fetch_reg(RS1(insn), regs); in array()
404 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); in bmask()
405 rs1 = fetch_reg(RS1(insn), regs); in bmask()
424 rs1 = fpd_regval(f, RS1(insn)); in bshuffle()
448 rs1 = fpd_regval(f, RS1(insn)); in pdist()
504 rs1 = fpd_regval(f, RS1(insn)); in pformat()
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/arch/arm/mach-vexpress/include/mach/
Ddebug-macro.S26 @ - all other (RS1 complaint) tiles use UART mapped
36 @ RS1 memory map
/arch/arm/boot/dts/
Dvexpress-v2m-rs1.dtsi9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
Dvexpress-v2m.dtsi13 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong