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Searched refs:S3C2410_DCLKCON_DCLK0_DIV (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-s3c24xx/include/mach/
Dregs-clock.h50 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) macro
/arch/arm/plat-s3c24xx/
Dclock-dclk.c110 data = S3C2410_DCLKCON_DCLK0_DIV(div) | in s3c24xx_set_dclk_rate()