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Searched refs:S5P64X0_CLK_DIV0 (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-s5p64x0/include/mach/
Dregs-clock.h27 #define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20) macro
92 #define ARM_CLK_DIV S5P64X0_CLK_DIV0
/arch/arm/mach-s5p64x0/
Dclock.c165 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
174 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
Dpm.c34 SAVE_ITEM(S5P64X0_CLK_DIV0),
Dclock-s5p6440.c101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
109 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
Dclock-s5p6450.c128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
136 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },