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Searched refs:S5P64X0_CLK_DIV1 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-s5p64x0/
Dclock-s5p6450.c101 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
450 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
459 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
477 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
490 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
502 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
514 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
Dclock-s5p6440.c389 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
Dpm.c35 SAVE_ITEM(S5P64X0_CLK_DIV1),
/arch/arm/mach-s5p64x0/include/mach/
Dregs-clock.h28 #define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24) macro