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Searched refs:S5P64X0_CLK_DIV3 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-s5p64x0/
Dclock-s5p6450.c143 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
151 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
160 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
168 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
432 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
468 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
Dclock-s5p6440.c117 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
398 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
407 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
Dpm.c37 SAVE_ITEM(S5P64X0_CLK_DIV3),
/arch/arm/mach-s5p64x0/include/mach/
Dregs-clock.h36 #define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40) macro