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Searched refs:S5P64X0_CLK_SRC0 (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-s5p64x0/
Dclock-s5p6450.c42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
449 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
458 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
476 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
489 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
501 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
513 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
524 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
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Dclock.c42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
Dclock-s5p6440.c388 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
428 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
463 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
475 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
487 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
Dpm.c32 SAVE_ITEM(S5P64X0_CLK_SRC0),
/arch/arm/mach-s5p64x0/include/mach/
Dregs-clock.h25 #define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C) macro