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Searched refs:S5P_CLK_DIV0 (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-s5pc100/include/mach/
Dregs-clock.h37 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
/arch/arm/mach-s5pv210/
Dclock.c77 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
85 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
93 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
101 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
120 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
1258 clkdiv0 = __raw_readl(S5P_CLK_DIV0); in s5pv210_setup_clocks()
Dpm.c44 SAVE_ITEM(S5P_CLK_DIV0),
/arch/arm/mach-s5pv210/include/mach/
Dregs-clock.h42 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
/arch/arm/mach-s5pc100/
Dclock.c125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },