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Searched refs:SIMM (Results 1 – 2 of 2) sorted by relevance

/arch/mips/mm/
Duasm.c29 SIMM = 0x010, enumerator
91 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
119 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
120 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
122 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
123 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
128 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
[all …]
/arch/powerpc/xmon/
Dppc-opc.c534 #define SIMM VD + 1 macro
538 #define UIMM SIMM + 1
2224 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2225 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2226 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2295 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2296 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },