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Searched refs:SRB_DEV0 (Results 1 – 2 of 2) sorted by relevance

/arch/mips/include/asm/sn/sn0/
Dip27.h53 #define SRB_DEV0 IE_IRQ0 /* 0x0400 */ macro
60 #define SR_IBIT_HI SRB_DEV0
/arch/mips/sgi-ip27/
Dip27-init.c144 set_c0_status(SRB_DEV0 | SRB_DEV1); in per_cpu_init()