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Searched refs:TIMER_VIRT (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-h720x/
Dcpu-h7201.c32 CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); in h7201_timer_interrupt()
49 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; in h7201_init_time()
50 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; in h7201_init_time()
51 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; in h7201_init_time()
52 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT; in h7201_init_time()
Dcpu-h7202.c113 mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); in h7202_timerx_demux_handler()
148 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; in __mask_timerx_irq()
163 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; in unmask_timerx_irq()
183 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; in h7202_init_time()
184 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; in h7202_init_time()
185 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; in h7202_init_time()
186 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT; in h7202_init_time()
Dcommon.c50 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH; in h720x_gettimeoffset()
/arch/arm/mach-h720x/include/mach/
Dhardware.h81 #define TIMER_VIRT (IO_VIRT + 0x25000) macro