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1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
3 
4 /*************************************************************************
5  * _REG relative to RSET_PERF
6  *************************************************************************/
7 
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG			0x0
10 #define REV_CHIPID_SHIFT		16
11 #define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT			0
13 #define REV_REVID_MASK			(0xffff << REV_REVID_SHIFT)
14 
15 /* Clock Control register */
16 #define PERF_CKCTL_REG			0x4
17 
18 #define CKCTL_6338_ADSLPHY_EN		(1 << 0)
19 #define CKCTL_6338_MPI_EN		(1 << 1)
20 #define CKCTL_6338_DRAM_EN		(1 << 2)
21 #define CKCTL_6338_ENET_EN		(1 << 4)
22 #define CKCTL_6338_USBS_EN		(1 << 4)
23 #define CKCTL_6338_SAR_EN		(1 << 5)
24 #define CKCTL_6338_SPI_EN		(1 << 9)
25 
26 #define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ADSLPHY_EN |	\
27 					CKCTL_6338_MPI_EN |		\
28 					CKCTL_6338_ENET_EN |		\
29 					CKCTL_6338_SAR_EN |		\
30 					CKCTL_6338_SPI_EN)
31 
32 #define CKCTL_6345_CPU_EN		(1 << 0)
33 #define CKCTL_6345_BUS_EN		(1 << 1)
34 #define CKCTL_6345_EBI_EN		(1 << 2)
35 #define CKCTL_6345_UART_EN		(1 << 3)
36 #define CKCTL_6345_ADSLPHY_EN		(1 << 4)
37 #define CKCTL_6345_ENET_EN		(1 << 7)
38 #define CKCTL_6345_USBH_EN		(1 << 8)
39 
40 #define CKCTL_6345_ALL_SAFE_EN		(CKCTL_6345_ENET_EN |	\
41 					CKCTL_6345_USBH_EN |	\
42 					CKCTL_6345_ADSLPHY_EN)
43 
44 #define CKCTL_6348_ADSLPHY_EN		(1 << 0)
45 #define CKCTL_6348_MPI_EN		(1 << 1)
46 #define CKCTL_6348_SDRAM_EN		(1 << 2)
47 #define CKCTL_6348_M2M_EN		(1 << 3)
48 #define CKCTL_6348_ENET_EN		(1 << 4)
49 #define CKCTL_6348_SAR_EN		(1 << 5)
50 #define CKCTL_6348_USBS_EN		(1 << 6)
51 #define CKCTL_6348_USBH_EN		(1 << 8)
52 #define CKCTL_6348_SPI_EN		(1 << 9)
53 
54 #define CKCTL_6348_ALL_SAFE_EN		(CKCTL_6348_ADSLPHY_EN |	\
55 					CKCTL_6348_M2M_EN |		\
56 					CKCTL_6348_ENET_EN |		\
57 					CKCTL_6348_SAR_EN |		\
58 					CKCTL_6348_USBS_EN |		\
59 					CKCTL_6348_USBH_EN |		\
60 					CKCTL_6348_SPI_EN)
61 
62 #define CKCTL_6358_ENET_EN		(1 << 4)
63 #define CKCTL_6358_ADSLPHY_EN		(1 << 5)
64 #define CKCTL_6358_PCM_EN		(1 << 8)
65 #define CKCTL_6358_SPI_EN		(1 << 9)
66 #define CKCTL_6358_USBS_EN		(1 << 10)
67 #define CKCTL_6358_SAR_EN		(1 << 11)
68 #define CKCTL_6358_EMUSB_EN		(1 << 17)
69 #define CKCTL_6358_ENET0_EN		(1 << 18)
70 #define CKCTL_6358_ENET1_EN		(1 << 19)
71 #define CKCTL_6358_USBSU_EN		(1 << 20)
72 #define CKCTL_6358_EPHY_EN		(1 << 21)
73 
74 #define CKCTL_6358_ALL_SAFE_EN		(CKCTL_6358_ENET_EN |		\
75 					CKCTL_6358_ADSLPHY_EN |		\
76 					CKCTL_6358_PCM_EN |		\
77 					CKCTL_6358_SPI_EN |		\
78 					CKCTL_6358_USBS_EN |		\
79 					CKCTL_6358_SAR_EN |		\
80 					CKCTL_6358_EMUSB_EN |		\
81 					CKCTL_6358_ENET0_EN |		\
82 					CKCTL_6358_ENET1_EN |		\
83 					CKCTL_6358_USBSU_EN |		\
84 					CKCTL_6358_EPHY_EN)
85 
86 #define CKCTL_6368_VDSL_QPROC_EN	(1 << 2)
87 #define CKCTL_6368_VDSL_AFE_EN		(1 << 3)
88 #define CKCTL_6368_VDSL_BONDING_EN	(1 << 4)
89 #define CKCTL_6368_VDSL_EN		(1 << 5)
90 #define CKCTL_6368_PHYMIPS_EN		(1 << 6)
91 #define CKCTL_6368_SWPKT_USB_EN		(1 << 7)
92 #define CKCTL_6368_SWPKT_SAR_EN		(1 << 8)
93 #define CKCTL_6368_SPI_CLK_EN		(1 << 9)
94 #define CKCTL_6368_USBD_CLK_EN		(1 << 10)
95 #define CKCTL_6368_SAR_CLK_EN		(1 << 11)
96 #define CKCTL_6368_ROBOSW_CLK_EN	(1 << 12)
97 #define CKCTL_6368_UTOPIA_CLK_EN	(1 << 13)
98 #define CKCTL_6368_PCM_CLK_EN		(1 << 14)
99 #define CKCTL_6368_USBH_CLK_EN		(1 << 15)
100 #define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
101 #define CKCTL_6368_NAND_CLK_EN		(1 << 17)
102 #define CKCTL_6368_IPSEC_CLK_EN		(1 << 17)
103 
104 #define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
105 					CKCTL_6368_SWPKT_SAR_EN |	\
106 					CKCTL_6368_SPI_CLK_EN |		\
107 					CKCTL_6368_USBD_CLK_EN |	\
108 					CKCTL_6368_SAR_CLK_EN |		\
109 					CKCTL_6368_ROBOSW_CLK_EN |	\
110 					CKCTL_6368_UTOPIA_CLK_EN |	\
111 					CKCTL_6368_PCM_CLK_EN |		\
112 					CKCTL_6368_USBH_CLK_EN |	\
113 					CKCTL_6368_DISABLE_GLESS_EN |	\
114 					CKCTL_6368_NAND_CLK_EN |	\
115 					CKCTL_6368_IPSEC_CLK_EN)
116 
117 /* System PLL Control register  */
118 #define PERF_SYS_PLL_CTL_REG		0x8
119 #define SYS_PLL_SOFT_RESET		0x1
120 
121 /* Interrupt Mask register */
122 #define PERF_IRQMASK_6338_REG		0xc
123 #define PERF_IRQMASK_6345_REG		0xc
124 #define PERF_IRQMASK_6348_REG		0xc
125 #define PERF_IRQMASK_6358_REG		0xc
126 #define PERF_IRQMASK_6368_REG		0x20
127 
128 /* Interrupt Status register */
129 #define PERF_IRQSTAT_6338_REG		0x10
130 #define PERF_IRQSTAT_6345_REG		0x10
131 #define PERF_IRQSTAT_6348_REG		0x10
132 #define PERF_IRQSTAT_6358_REG		0x10
133 #define PERF_IRQSTAT_6368_REG		0x28
134 
135 /* External Interrupt Configuration register */
136 #define PERF_EXTIRQ_CFG_REG_6338	0x14
137 #define PERF_EXTIRQ_CFG_REG_6348	0x14
138 #define PERF_EXTIRQ_CFG_REG_6358	0x14
139 #define PERF_EXTIRQ_CFG_REG_6368	0x18
140 
141 #define PERF_EXTIRQ_CFG_REG2_6368	0x1c
142 
143 /* for 6348 only */
144 #define EXTIRQ_CFG_SENSE_6348(x)	(1 << (x))
145 #define EXTIRQ_CFG_STAT_6348(x)		(1 << (x + 5))
146 #define EXTIRQ_CFG_CLEAR_6348(x)	(1 << (x + 10))
147 #define EXTIRQ_CFG_MASK_6348(x)		(1 << (x + 15))
148 #define EXTIRQ_CFG_BOTHEDGE_6348(x)	(1 << (x + 20))
149 #define EXTIRQ_CFG_LEVELSENSE_6348(x)	(1 << (x + 25))
150 #define EXTIRQ_CFG_CLEAR_ALL_6348	(0xf << 10)
151 #define EXTIRQ_CFG_MASK_ALL_6348	(0xf << 15)
152 
153 /* for all others */
154 #define EXTIRQ_CFG_SENSE(x)		(1 << (x))
155 #define EXTIRQ_CFG_STAT(x)		(1 << (x + 4))
156 #define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 8))
157 #define EXTIRQ_CFG_MASK(x)		(1 << (x + 12))
158 #define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 16))
159 #define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 20))
160 #define EXTIRQ_CFG_CLEAR_ALL		(0xf << 8)
161 #define EXTIRQ_CFG_MASK_ALL		(0xf << 12)
162 
163 /* Soft Reset register */
164 #define PERF_SOFTRESET_REG		0x28
165 #define PERF_SOFTRESET_6368_REG		0x10
166 
167 #define SOFTRESET_6338_SPI_MASK		(1 << 0)
168 #define SOFTRESET_6338_ENET_MASK	(1 << 2)
169 #define SOFTRESET_6338_USBH_MASK	(1 << 3)
170 #define SOFTRESET_6338_USBS_MASK	(1 << 4)
171 #define SOFTRESET_6338_ADSL_MASK	(1 << 5)
172 #define SOFTRESET_6338_DMAMEM_MASK	(1 << 6)
173 #define SOFTRESET_6338_SAR_MASK		(1 << 7)
174 #define SOFTRESET_6338_ACLC_MASK	(1 << 8)
175 #define SOFTRESET_6338_ADSLMIPSPLL_MASK	(1 << 10)
176 #define SOFTRESET_6338_ALL	 (SOFTRESET_6338_SPI_MASK |		\
177 				  SOFTRESET_6338_ENET_MASK |		\
178 				  SOFTRESET_6338_USBH_MASK |		\
179 				  SOFTRESET_6338_USBS_MASK |		\
180 				  SOFTRESET_6338_ADSL_MASK |		\
181 				  SOFTRESET_6338_DMAMEM_MASK |		\
182 				  SOFTRESET_6338_SAR_MASK |		\
183 				  SOFTRESET_6338_ACLC_MASK |		\
184 				  SOFTRESET_6338_ADSLMIPSPLL_MASK)
185 
186 #define SOFTRESET_6348_SPI_MASK		(1 << 0)
187 #define SOFTRESET_6348_ENET_MASK	(1 << 2)
188 #define SOFTRESET_6348_USBH_MASK	(1 << 3)
189 #define SOFTRESET_6348_USBS_MASK	(1 << 4)
190 #define SOFTRESET_6348_ADSL_MASK	(1 << 5)
191 #define SOFTRESET_6348_DMAMEM_MASK	(1 << 6)
192 #define SOFTRESET_6348_SAR_MASK		(1 << 7)
193 #define SOFTRESET_6348_ACLC_MASK	(1 << 8)
194 #define SOFTRESET_6348_ADSLMIPSPLL_MASK	(1 << 10)
195 
196 #define SOFTRESET_6348_ALL	 (SOFTRESET_6348_SPI_MASK |		\
197 				  SOFTRESET_6348_ENET_MASK |		\
198 				  SOFTRESET_6348_USBH_MASK |		\
199 				  SOFTRESET_6348_USBS_MASK |		\
200 				  SOFTRESET_6348_ADSL_MASK |		\
201 				  SOFTRESET_6348_DMAMEM_MASK |		\
202 				  SOFTRESET_6348_SAR_MASK |		\
203 				  SOFTRESET_6348_ACLC_MASK |		\
204 				  SOFTRESET_6348_ADSLMIPSPLL_MASK)
205 
206 #define SOFTRESET_6368_SPI_MASK		(1 << 0)
207 #define SOFTRESET_6368_MPI_MASK		(1 << 3)
208 #define SOFTRESET_6368_EPHY_MASK	(1 << 6)
209 #define SOFTRESET_6368_SAR_MASK		(1 << 7)
210 #define SOFTRESET_6368_ENETSW_MASK	(1 << 10)
211 #define SOFTRESET_6368_USBS_MASK	(1 << 11)
212 #define SOFTRESET_6368_USBH_MASK	(1 << 12)
213 #define SOFTRESET_6368_PCM_MASK		(1 << 13)
214 
215 /* MIPS PLL control register */
216 #define PERF_MIPSPLLCTL_REG		0x34
217 #define MIPSPLLCTL_N1_SHIFT		20
218 #define MIPSPLLCTL_N1_MASK		(0x7 << MIPSPLLCTL_N1_SHIFT)
219 #define MIPSPLLCTL_N2_SHIFT		15
220 #define MIPSPLLCTL_N2_MASK		(0x1f << MIPSPLLCTL_N2_SHIFT)
221 #define MIPSPLLCTL_M1REF_SHIFT		12
222 #define MIPSPLLCTL_M1REF_MASK		(0x7 << MIPSPLLCTL_M1REF_SHIFT)
223 #define MIPSPLLCTL_M2REF_SHIFT		9
224 #define MIPSPLLCTL_M2REF_MASK		(0x7 << MIPSPLLCTL_M2REF_SHIFT)
225 #define MIPSPLLCTL_M1CPU_SHIFT		6
226 #define MIPSPLLCTL_M1CPU_MASK		(0x7 << MIPSPLLCTL_M1CPU_SHIFT)
227 #define MIPSPLLCTL_M1BUS_SHIFT		3
228 #define MIPSPLLCTL_M1BUS_MASK		(0x7 << MIPSPLLCTL_M1BUS_SHIFT)
229 #define MIPSPLLCTL_M2BUS_SHIFT		0
230 #define MIPSPLLCTL_M2BUS_MASK		(0x7 << MIPSPLLCTL_M2BUS_SHIFT)
231 
232 /* ADSL PHY PLL Control register */
233 #define PERF_ADSLPLLCTL_REG		0x38
234 #define ADSLPLLCTL_N1_SHIFT		20
235 #define ADSLPLLCTL_N1_MASK		(0x7 << ADSLPLLCTL_N1_SHIFT)
236 #define ADSLPLLCTL_N2_SHIFT		15
237 #define ADSLPLLCTL_N2_MASK		(0x1f << ADSLPLLCTL_N2_SHIFT)
238 #define ADSLPLLCTL_M1REF_SHIFT		12
239 #define ADSLPLLCTL_M1REF_MASK		(0x7 << ADSLPLLCTL_M1REF_SHIFT)
240 #define ADSLPLLCTL_M2REF_SHIFT		9
241 #define ADSLPLLCTL_M2REF_MASK		(0x7 << ADSLPLLCTL_M2REF_SHIFT)
242 #define ADSLPLLCTL_M1CPU_SHIFT		6
243 #define ADSLPLLCTL_M1CPU_MASK		(0x7 << ADSLPLLCTL_M1CPU_SHIFT)
244 #define ADSLPLLCTL_M1BUS_SHIFT		3
245 #define ADSLPLLCTL_M1BUS_MASK		(0x7 << ADSLPLLCTL_M1BUS_SHIFT)
246 #define ADSLPLLCTL_M2BUS_SHIFT		0
247 #define ADSLPLLCTL_M2BUS_MASK		(0x7 << ADSLPLLCTL_M2BUS_SHIFT)
248 
249 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus)	\
250 				(((n1) << ADSLPLLCTL_N1_SHIFT) |	\
251 				((n2) << ADSLPLLCTL_N2_SHIFT) |		\
252 				((m1ref) << ADSLPLLCTL_M1REF_SHIFT) |	\
253 				((m2ref) << ADSLPLLCTL_M2REF_SHIFT) |	\
254 				((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) |	\
255 				((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) |	\
256 				((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
257 
258 
259 /*************************************************************************
260  * _REG relative to RSET_TIMER
261  *************************************************************************/
262 
263 #define BCM63XX_TIMER_COUNT		4
264 #define TIMER_T0_ID			0
265 #define TIMER_T1_ID			1
266 #define TIMER_T2_ID			2
267 #define TIMER_WDT_ID			3
268 
269 /* Timer irqstat register */
270 #define TIMER_IRQSTAT_REG		0
271 #define TIMER_IRQSTAT_TIMER_CAUSE(x)	(1 << (x))
272 #define TIMER_IRQSTAT_TIMER0_CAUSE	(1 << 0)
273 #define TIMER_IRQSTAT_TIMER1_CAUSE	(1 << 1)
274 #define TIMER_IRQSTAT_TIMER2_CAUSE	(1 << 2)
275 #define TIMER_IRQSTAT_WDT_CAUSE		(1 << 3)
276 #define TIMER_IRQSTAT_TIMER_IR_EN(x)	(1 << ((x) + 8))
277 #define TIMER_IRQSTAT_TIMER0_IR_EN	(1 << 8)
278 #define TIMER_IRQSTAT_TIMER1_IR_EN	(1 << 9)
279 #define TIMER_IRQSTAT_TIMER2_IR_EN	(1 << 10)
280 
281 /* Timer control register */
282 #define TIMER_CTLx_REG(x)		(0x4 + (x * 4))
283 #define TIMER_CTL0_REG			0x4
284 #define TIMER_CTL1_REG			0x8
285 #define TIMER_CTL2_REG			0xC
286 #define TIMER_CTL_COUNTDOWN_MASK	(0x3fffffff)
287 #define TIMER_CTL_MONOTONIC_MASK	(1 << 30)
288 #define TIMER_CTL_ENABLE_MASK		(1 << 31)
289 
290 
291 /*************************************************************************
292  * _REG relative to RSET_WDT
293  *************************************************************************/
294 
295 /* Watchdog default count register */
296 #define WDT_DEFVAL_REG			0x0
297 
298 /* Watchdog control register */
299 #define WDT_CTL_REG			0x4
300 
301 /* Watchdog control register constants */
302 #define WDT_START_1			(0xff00)
303 #define WDT_START_2			(0x00ff)
304 #define WDT_STOP_1			(0xee00)
305 #define WDT_STOP_2			(0x00ee)
306 
307 /* Watchdog reset length register */
308 #define WDT_RSTLEN_REG			0x8
309 
310 
311 /*************************************************************************
312  * _REG relative to RSET_UARTx
313  *************************************************************************/
314 
315 /* UART Control Register */
316 #define UART_CTL_REG			0x0
317 #define UART_CTL_RXTMOUTCNT_SHIFT	0
318 #define UART_CTL_RXTMOUTCNT_MASK	(0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
319 #define UART_CTL_RSTTXDN_SHIFT		5
320 #define UART_CTL_RSTTXDN_MASK		(1 << UART_CTL_RSTTXDN_SHIFT)
321 #define UART_CTL_RSTRXFIFO_SHIFT		6
322 #define UART_CTL_RSTRXFIFO_MASK		(1 << UART_CTL_RSTRXFIFO_SHIFT)
323 #define UART_CTL_RSTTXFIFO_SHIFT		7
324 #define UART_CTL_RSTTXFIFO_MASK		(1 << UART_CTL_RSTTXFIFO_SHIFT)
325 #define UART_CTL_STOPBITS_SHIFT		8
326 #define UART_CTL_STOPBITS_MASK		(0xf << UART_CTL_STOPBITS_SHIFT)
327 #define UART_CTL_STOPBITS_1		(0x7 << UART_CTL_STOPBITS_SHIFT)
328 #define UART_CTL_STOPBITS_2		(0xf << UART_CTL_STOPBITS_SHIFT)
329 #define UART_CTL_BITSPERSYM_SHIFT	12
330 #define UART_CTL_BITSPERSYM_MASK	(0x3 << UART_CTL_BITSPERSYM_SHIFT)
331 #define UART_CTL_XMITBRK_SHIFT		14
332 #define UART_CTL_XMITBRK_MASK		(1 << UART_CTL_XMITBRK_SHIFT)
333 #define UART_CTL_RSVD_SHIFT		15
334 #define UART_CTL_RSVD_MASK		(1 << UART_CTL_RSVD_SHIFT)
335 #define UART_CTL_RXPAREVEN_SHIFT		16
336 #define UART_CTL_RXPAREVEN_MASK		(1 << UART_CTL_RXPAREVEN_SHIFT)
337 #define UART_CTL_RXPAREN_SHIFT		17
338 #define UART_CTL_RXPAREN_MASK		(1 << UART_CTL_RXPAREN_SHIFT)
339 #define UART_CTL_TXPAREVEN_SHIFT		18
340 #define UART_CTL_TXPAREVEN_MASK		(1 << UART_CTL_TXPAREVEN_SHIFT)
341 #define UART_CTL_TXPAREN_SHIFT		18
342 #define UART_CTL_TXPAREN_MASK		(1 << UART_CTL_TXPAREN_SHIFT)
343 #define UART_CTL_LOOPBACK_SHIFT		20
344 #define UART_CTL_LOOPBACK_MASK		(1 << UART_CTL_LOOPBACK_SHIFT)
345 #define UART_CTL_RXEN_SHIFT		21
346 #define UART_CTL_RXEN_MASK		(1 << UART_CTL_RXEN_SHIFT)
347 #define UART_CTL_TXEN_SHIFT		22
348 #define UART_CTL_TXEN_MASK		(1 << UART_CTL_TXEN_SHIFT)
349 #define UART_CTL_BRGEN_SHIFT		23
350 #define UART_CTL_BRGEN_MASK		(1 << UART_CTL_BRGEN_SHIFT)
351 
352 /* UART Baudword register */
353 #define UART_BAUD_REG			0x4
354 
355 /* UART Misc Control register */
356 #define UART_MCTL_REG			0x8
357 #define UART_MCTL_DTR_SHIFT		0
358 #define UART_MCTL_DTR_MASK		(1 << UART_MCTL_DTR_SHIFT)
359 #define UART_MCTL_RTS_SHIFT		1
360 #define UART_MCTL_RTS_MASK		(1 << UART_MCTL_RTS_SHIFT)
361 #define UART_MCTL_RXFIFOTHRESH_SHIFT	8
362 #define UART_MCTL_RXFIFOTHRESH_MASK	(0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
363 #define UART_MCTL_TXFIFOTHRESH_SHIFT	12
364 #define UART_MCTL_TXFIFOTHRESH_MASK	(0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
365 #define UART_MCTL_RXFIFOFILL_SHIFT	16
366 #define UART_MCTL_RXFIFOFILL_MASK	(0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
367 #define UART_MCTL_TXFIFOFILL_SHIFT	24
368 #define UART_MCTL_TXFIFOFILL_MASK	(0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
369 
370 /* UART External Input Configuration register */
371 #define UART_EXTINP_REG			0xc
372 #define UART_EXTINP_RI_SHIFT		0
373 #define UART_EXTINP_RI_MASK		(1 << UART_EXTINP_RI_SHIFT)
374 #define UART_EXTINP_CTS_SHIFT		1
375 #define UART_EXTINP_CTS_MASK		(1 << UART_EXTINP_CTS_SHIFT)
376 #define UART_EXTINP_DCD_SHIFT		2
377 #define UART_EXTINP_DCD_MASK		(1 << UART_EXTINP_DCD_SHIFT)
378 #define UART_EXTINP_DSR_SHIFT		3
379 #define UART_EXTINP_DSR_MASK		(1 << UART_EXTINP_DSR_SHIFT)
380 #define UART_EXTINP_IRSTAT(x)		(1 << (x + 4))
381 #define UART_EXTINP_IRMASK(x)		(1 << (x + 8))
382 #define UART_EXTINP_IR_RI		0
383 #define UART_EXTINP_IR_CTS		1
384 #define UART_EXTINP_IR_DCD		2
385 #define UART_EXTINP_IR_DSR		3
386 #define UART_EXTINP_RI_NOSENSE_SHIFT	16
387 #define UART_EXTINP_RI_NOSENSE_MASK	(1 << UART_EXTINP_RI_NOSENSE_SHIFT)
388 #define UART_EXTINP_CTS_NOSENSE_SHIFT	17
389 #define UART_EXTINP_CTS_NOSENSE_MASK	(1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
390 #define UART_EXTINP_DCD_NOSENSE_SHIFT	18
391 #define UART_EXTINP_DCD_NOSENSE_MASK	(1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
392 #define UART_EXTINP_DSR_NOSENSE_SHIFT	19
393 #define UART_EXTINP_DSR_NOSENSE_MASK	(1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
394 
395 /* UART Interrupt register */
396 #define UART_IR_REG			0x10
397 #define UART_IR_MASK(x)			(1 << (x + 16))
398 #define UART_IR_STAT(x)			(1 << (x))
399 #define UART_IR_EXTIP			0
400 #define UART_IR_TXUNDER			1
401 #define UART_IR_TXOVER			2
402 #define UART_IR_TXTRESH			3
403 #define UART_IR_TXRDLATCH		4
404 #define UART_IR_TXEMPTY			5
405 #define UART_IR_RXUNDER			6
406 #define UART_IR_RXOVER			7
407 #define UART_IR_RXTIMEOUT		8
408 #define UART_IR_RXFULL			9
409 #define UART_IR_RXTHRESH		10
410 #define UART_IR_RXNOTEMPTY		11
411 #define UART_IR_RXFRAMEERR		12
412 #define UART_IR_RXPARERR		13
413 #define UART_IR_RXBRK			14
414 #define UART_IR_TXDONE			15
415 
416 /* UART Fifo register */
417 #define UART_FIFO_REG			0x14
418 #define UART_FIFO_VALID_SHIFT		0
419 #define UART_FIFO_VALID_MASK		0xff
420 #define UART_FIFO_FRAMEERR_SHIFT	8
421 #define UART_FIFO_FRAMEERR_MASK		(1 << UART_FIFO_FRAMEERR_SHIFT)
422 #define UART_FIFO_PARERR_SHIFT		9
423 #define UART_FIFO_PARERR_MASK		(1 << UART_FIFO_PARERR_SHIFT)
424 #define UART_FIFO_BRKDET_SHIFT		10
425 #define UART_FIFO_BRKDET_MASK		(1 << UART_FIFO_BRKDET_SHIFT)
426 #define UART_FIFO_ANYERR_MASK		(UART_FIFO_FRAMEERR_MASK |	\
427 					UART_FIFO_PARERR_MASK |		\
428 					UART_FIFO_BRKDET_MASK)
429 
430 
431 /*************************************************************************
432  * _REG relative to RSET_GPIO
433  *************************************************************************/
434 
435 /* GPIO registers */
436 #define GPIO_CTL_HI_REG			0x0
437 #define GPIO_CTL_LO_REG			0x4
438 #define GPIO_DATA_HI_REG		0x8
439 #define GPIO_DATA_LO_REG		0xC
440 #define GPIO_DATA_LO_REG_6345		0x8
441 
442 /* GPIO mux registers and constants */
443 #define GPIO_MODE_REG			0x18
444 
445 #define GPIO_MODE_6348_G4_DIAG		0x00090000
446 #define GPIO_MODE_6348_G4_UTOPIA	0x00080000
447 #define GPIO_MODE_6348_G4_LEGACY_LED	0x00030000
448 #define GPIO_MODE_6348_G4_MII_SNOOP	0x00020000
449 #define GPIO_MODE_6348_G4_EXT_EPHY	0x00010000
450 #define GPIO_MODE_6348_G3_DIAG		0x00009000
451 #define GPIO_MODE_6348_G3_UTOPIA	0x00008000
452 #define GPIO_MODE_6348_G3_EXT_MII	0x00007000
453 #define GPIO_MODE_6348_G2_DIAG		0x00000900
454 #define GPIO_MODE_6348_G2_PCI		0x00000500
455 #define GPIO_MODE_6348_G1_DIAG		0x00000090
456 #define GPIO_MODE_6348_G1_UTOPIA	0x00000080
457 #define GPIO_MODE_6348_G1_SPI_UART	0x00000060
458 #define GPIO_MODE_6348_G1_SPI_MASTER	0x00000060
459 #define GPIO_MODE_6348_G1_MII_PCCARD	0x00000040
460 #define GPIO_MODE_6348_G1_MII_SNOOP	0x00000020
461 #define GPIO_MODE_6348_G1_EXT_EPHY	0x00000010
462 #define GPIO_MODE_6348_G0_DIAG		0x00000009
463 #define GPIO_MODE_6348_G0_EXT_MII	0x00000007
464 
465 #define GPIO_MODE_6358_EXTRACS		(1 << 5)
466 #define GPIO_MODE_6358_UART1		(1 << 6)
467 #define GPIO_MODE_6358_EXTRA_SPI_SS	(1 << 7)
468 #define GPIO_MODE_6358_SERIAL_LED	(1 << 10)
469 #define GPIO_MODE_6358_UTOPIA		(1 << 12)
470 
471 #define GPIO_MODE_6368_ANALOG_AFE_0	(1 << 0)
472 #define GPIO_MODE_6368_ANALOG_AFE_1	(1 << 1)
473 #define GPIO_MODE_6368_SYS_IRQ		(1 << 2)
474 #define GPIO_MODE_6368_SERIAL_LED_DATA	(1 << 3)
475 #define GPIO_MODE_6368_SERIAL_LED_CLK	(1 << 4)
476 #define GPIO_MODE_6368_INET_LED		(1 << 5)
477 #define GPIO_MODE_6368_EPHY0_LED	(1 << 6)
478 #define GPIO_MODE_6368_EPHY1_LED	(1 << 7)
479 #define GPIO_MODE_6368_EPHY2_LED	(1 << 8)
480 #define GPIO_MODE_6368_EPHY3_LED	(1 << 9)
481 #define GPIO_MODE_6368_ROBOSW_LED_DAT	(1 << 10)
482 #define GPIO_MODE_6368_ROBOSW_LED_CLK	(1 << 11)
483 #define GPIO_MODE_6368_ROBOSW_LED0	(1 << 12)
484 #define GPIO_MODE_6368_ROBOSW_LED1	(1 << 13)
485 #define GPIO_MODE_6368_USBD_LED		(1 << 14)
486 #define GPIO_MODE_6368_NTR_PULSE	(1 << 15)
487 #define GPIO_MODE_6368_PCI_REQ1		(1 << 16)
488 #define GPIO_MODE_6368_PCI_GNT1		(1 << 17)
489 #define GPIO_MODE_6368_PCI_INTB		(1 << 18)
490 #define GPIO_MODE_6368_PCI_REQ0		(1 << 19)
491 #define GPIO_MODE_6368_PCI_GNT0		(1 << 20)
492 #define GPIO_MODE_6368_PCMCIA_CD1	(1 << 22)
493 #define GPIO_MODE_6368_PCMCIA_CD2	(1 << 23)
494 #define GPIO_MODE_6368_PCMCIA_VS1	(1 << 24)
495 #define GPIO_MODE_6368_PCMCIA_VS2	(1 << 25)
496 #define GPIO_MODE_6368_EBI_CS2		(1 << 26)
497 #define GPIO_MODE_6368_EBI_CS3		(1 << 27)
498 #define GPIO_MODE_6368_SPI_SSN2		(1 << 28)
499 #define GPIO_MODE_6368_SPI_SSN3		(1 << 29)
500 #define GPIO_MODE_6368_SPI_SSN4		(1 << 30)
501 #define GPIO_MODE_6368_SPI_SSN5		(1 << 31)
502 
503 
504 #define GPIO_BASEMODE_6368_REG		0x38
505 #define GPIO_BASEMODE_6368_UART2	0x1
506 #define GPIO_BASEMODE_6368_GPIO		0x0
507 #define GPIO_BASEMODE_6368_MASK		0x7
508 /* those bits must be kept as read in gpio basemode register*/
509 
510 /*************************************************************************
511  * _REG relative to RSET_ENET
512  *************************************************************************/
513 
514 /* Receiver Configuration register */
515 #define ENET_RXCFG_REG			0x0
516 #define ENET_RXCFG_ALLMCAST_SHIFT	1
517 #define ENET_RXCFG_ALLMCAST_MASK	(1 << ENET_RXCFG_ALLMCAST_SHIFT)
518 #define ENET_RXCFG_PROMISC_SHIFT	3
519 #define ENET_RXCFG_PROMISC_MASK		(1 << ENET_RXCFG_PROMISC_SHIFT)
520 #define ENET_RXCFG_LOOPBACK_SHIFT	4
521 #define ENET_RXCFG_LOOPBACK_MASK	(1 << ENET_RXCFG_LOOPBACK_SHIFT)
522 #define ENET_RXCFG_ENFLOW_SHIFT		5
523 #define ENET_RXCFG_ENFLOW_MASK		(1 << ENET_RXCFG_ENFLOW_SHIFT)
524 
525 /* Receive Maximum Length register */
526 #define ENET_RXMAXLEN_REG		0x4
527 #define ENET_RXMAXLEN_SHIFT		0
528 #define ENET_RXMAXLEN_MASK		(0x7ff << ENET_RXMAXLEN_SHIFT)
529 
530 /* Transmit Maximum Length register */
531 #define ENET_TXMAXLEN_REG		0x8
532 #define ENET_TXMAXLEN_SHIFT		0
533 #define ENET_TXMAXLEN_MASK		(0x7ff << ENET_TXMAXLEN_SHIFT)
534 
535 /* MII Status/Control register */
536 #define ENET_MIISC_REG			0x10
537 #define ENET_MIISC_MDCFREQDIV_SHIFT	0
538 #define ENET_MIISC_MDCFREQDIV_MASK	(0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
539 #define ENET_MIISC_PREAMBLEEN_SHIFT	7
540 #define ENET_MIISC_PREAMBLEEN_MASK	(1 << ENET_MIISC_PREAMBLEEN_SHIFT)
541 
542 /* MII Data register */
543 #define ENET_MIIDATA_REG		0x14
544 #define ENET_MIIDATA_DATA_SHIFT		0
545 #define ENET_MIIDATA_DATA_MASK		(0xffff << ENET_MIIDATA_DATA_SHIFT)
546 #define ENET_MIIDATA_TA_SHIFT		16
547 #define ENET_MIIDATA_TA_MASK		(0x3 << ENET_MIIDATA_TA_SHIFT)
548 #define ENET_MIIDATA_REG_SHIFT		18
549 #define ENET_MIIDATA_REG_MASK		(0x1f << ENET_MIIDATA_REG_SHIFT)
550 #define ENET_MIIDATA_PHYID_SHIFT	23
551 #define ENET_MIIDATA_PHYID_MASK		(0x1f << ENET_MIIDATA_PHYID_SHIFT)
552 #define ENET_MIIDATA_OP_READ_MASK	(0x6 << 28)
553 #define ENET_MIIDATA_OP_WRITE_MASK	(0x5 << 28)
554 
555 /* Ethernet Interrupt Mask register */
556 #define ENET_IRMASK_REG			0x18
557 
558 /* Ethernet Interrupt register */
559 #define ENET_IR_REG			0x1c
560 #define ENET_IR_MII			(1 << 0)
561 #define ENET_IR_MIB			(1 << 1)
562 #define ENET_IR_FLOWC			(1 << 2)
563 
564 /* Ethernet Control register */
565 #define ENET_CTL_REG			0x2c
566 #define ENET_CTL_ENABLE_SHIFT		0
567 #define ENET_CTL_ENABLE_MASK		(1 << ENET_CTL_ENABLE_SHIFT)
568 #define ENET_CTL_DISABLE_SHIFT		1
569 #define ENET_CTL_DISABLE_MASK		(1 << ENET_CTL_DISABLE_SHIFT)
570 #define ENET_CTL_SRESET_SHIFT		2
571 #define ENET_CTL_SRESET_MASK		(1 << ENET_CTL_SRESET_SHIFT)
572 #define ENET_CTL_EPHYSEL_SHIFT		3
573 #define ENET_CTL_EPHYSEL_MASK		(1 << ENET_CTL_EPHYSEL_SHIFT)
574 
575 /* Transmit Control register */
576 #define ENET_TXCTL_REG			0x30
577 #define ENET_TXCTL_FD_SHIFT		0
578 #define ENET_TXCTL_FD_MASK		(1 << ENET_TXCTL_FD_SHIFT)
579 
580 /* Transmit Watermask register */
581 #define ENET_TXWMARK_REG		0x34
582 #define ENET_TXWMARK_WM_SHIFT		0
583 #define ENET_TXWMARK_WM_MASK		(0x3f << ENET_TXWMARK_WM_SHIFT)
584 
585 /* MIB Control register */
586 #define ENET_MIBCTL_REG			0x38
587 #define ENET_MIBCTL_RDCLEAR_SHIFT	0
588 #define ENET_MIBCTL_RDCLEAR_MASK	(1 << ENET_MIBCTL_RDCLEAR_SHIFT)
589 
590 /* Perfect Match Data Low register */
591 #define ENET_PML_REG(x)			(0x58 + (x) * 8)
592 #define ENET_PMH_REG(x)			(0x5c + (x) * 8)
593 #define ENET_PMH_DATAVALID_SHIFT	16
594 #define ENET_PMH_DATAVALID_MASK		(1 << ENET_PMH_DATAVALID_SHIFT)
595 
596 /* MIB register */
597 #define ENET_MIB_REG(x)			(0x200 + (x) * 4)
598 #define ENET_MIB_REG_COUNT		55
599 
600 
601 /*************************************************************************
602  * _REG relative to RSET_ENETDMA
603  *************************************************************************/
604 
605 /* Controller Configuration Register */
606 #define ENETDMA_CFG_REG			(0x0)
607 #define ENETDMA_CFG_EN_SHIFT		0
608 #define ENETDMA_CFG_EN_MASK		(1 << ENETDMA_CFG_EN_SHIFT)
609 #define ENETDMA_CFG_FLOWCH_MASK(x)	(1 << ((x >> 1) + 1))
610 
611 /* Flow Control Descriptor Low Threshold register */
612 #define ENETDMA_FLOWCL_REG(x)		(0x4 + (x) * 6)
613 
614 /* Flow Control Descriptor High Threshold register */
615 #define ENETDMA_FLOWCH_REG(x)		(0x8 + (x) * 6)
616 
617 /* Flow Control Descriptor Buffer Alloca Threshold register */
618 #define ENETDMA_BUFALLOC_REG(x)		(0xc + (x) * 6)
619 #define ENETDMA_BUFALLOC_FORCE_SHIFT	31
620 #define ENETDMA_BUFALLOC_FORCE_MASK	(1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
621 
622 /* Channel Configuration register */
623 #define ENETDMA_CHANCFG_REG(x)		(0x100 + (x) * 0x10)
624 #define ENETDMA_CHANCFG_EN_SHIFT	0
625 #define ENETDMA_CHANCFG_EN_MASK		(1 << ENETDMA_CHANCFG_EN_SHIFT)
626 #define ENETDMA_CHANCFG_PKTHALT_SHIFT	1
627 #define ENETDMA_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
628 
629 /* Interrupt Control/Status register */
630 #define ENETDMA_IR_REG(x)		(0x104 + (x) * 0x10)
631 #define ENETDMA_IR_BUFDONE_MASK		(1 << 0)
632 #define ENETDMA_IR_PKTDONE_MASK		(1 << 1)
633 #define ENETDMA_IR_NOTOWNER_MASK	(1 << 2)
634 
635 /* Interrupt Mask register */
636 #define ENETDMA_IRMASK_REG(x)		(0x108 + (x) * 0x10)
637 
638 /* Maximum Burst Length */
639 #define ENETDMA_MAXBURST_REG(x)		(0x10C + (x) * 0x10)
640 
641 /* Ring Start Address register */
642 #define ENETDMA_RSTART_REG(x)		(0x200 + (x) * 0x10)
643 
644 /* State Ram Word 2 */
645 #define ENETDMA_SRAM2_REG(x)		(0x204 + (x) * 0x10)
646 
647 /* State Ram Word 3 */
648 #define ENETDMA_SRAM3_REG(x)		(0x208 + (x) * 0x10)
649 
650 /* State Ram Word 4 */
651 #define ENETDMA_SRAM4_REG(x)		(0x20c + (x) * 0x10)
652 
653 
654 /*************************************************************************
655  * _REG relative to RSET_ENETDMAC
656  *************************************************************************/
657 
658 /* Channel Configuration register */
659 #define ENETDMAC_CHANCFG_REG(x)		((x) * 0x10)
660 #define ENETDMAC_CHANCFG_EN_SHIFT	0
661 #define ENETDMAC_CHANCFG_EN_MASK	(1 << ENETDMA_CHANCFG_EN_SHIFT)
662 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT	1
663 #define ENETDMAC_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
664 
665 /* Interrupt Control/Status register */
666 #define ENETDMAC_IR_REG(x)		(0x4 + (x) * 0x10)
667 #define ENETDMAC_IR_BUFDONE_MASK	(1 << 0)
668 #define ENETDMAC_IR_PKTDONE_MASK	(1 << 1)
669 #define ENETDMAC_IR_NOTOWNER_MASK	(1 << 2)
670 
671 /* Interrupt Mask register */
672 #define ENETDMAC_IRMASK_REG(x)		(0x8 + (x) * 0x10)
673 
674 /* Maximum Burst Length */
675 #define ENETDMAC_MAXBURST_REG(x)	(0xc + (x) * 0x10)
676 
677 
678 /*************************************************************************
679  * _REG relative to RSET_ENETDMAS
680  *************************************************************************/
681 
682 /* Ring Start Address register */
683 #define ENETDMAS_RSTART_REG(x)		((x) * 0x10)
684 
685 /* State Ram Word 2 */
686 #define ENETDMAS_SRAM2_REG(x)		(0x4 + (x) * 0x10)
687 
688 /* State Ram Word 3 */
689 #define ENETDMAS_SRAM3_REG(x)		(0x8 + (x) * 0x10)
690 
691 /* State Ram Word 4 */
692 #define ENETDMAS_SRAM4_REG(x)		(0xc + (x) * 0x10)
693 
694 
695 /*************************************************************************
696  * _REG relative to RSET_ENETSW
697  *************************************************************************/
698 
699 /* MIB register */
700 #define ENETSW_MIB_REG(x)		(0x2800 + (x) * 4)
701 #define ENETSW_MIB_REG_COUNT		47
702 
703 
704 /*************************************************************************
705  * _REG relative to RSET_OHCI_PRIV
706  *************************************************************************/
707 
708 #define OHCI_PRIV_REG			0x0
709 #define OHCI_PRIV_PORT1_HOST_SHIFT	0
710 #define OHCI_PRIV_PORT1_HOST_MASK	(1 << OHCI_PRIV_PORT1_HOST_SHIFT)
711 #define OHCI_PRIV_REG_SWAP_SHIFT	3
712 #define OHCI_PRIV_REG_SWAP_MASK		(1 << OHCI_PRIV_REG_SWAP_SHIFT)
713 
714 
715 /*************************************************************************
716  * _REG relative to RSET_USBH_PRIV
717  *************************************************************************/
718 
719 #define USBH_PRIV_SWAP_6358_REG		0x0
720 #define USBH_PRIV_SWAP_6368_REG		0x1c
721 
722 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT	4
723 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
724 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT	3
725 #define USBH_PRIV_SWAP_EHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
726 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT	1
727 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
728 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT	0
729 #define USBH_PRIV_SWAP_OHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
730 
731 #define USBH_PRIV_TEST_6358_REG		0x24
732 #define USBH_PRIV_TEST_6368_REG		0x14
733 
734 #define USBH_PRIV_SETUP_6368_REG	0x28
735 #define USBH_PRIV_SETUP_IOC_SHIFT	4
736 #define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
737 
738 
739 
740 /*************************************************************************
741  * _REG relative to RSET_MPI
742  *************************************************************************/
743 
744 /* well known (hard wired) chip select */
745 #define MPI_CS_PCMCIA_COMMON		4
746 #define MPI_CS_PCMCIA_ATTR		5
747 #define MPI_CS_PCMCIA_IO		6
748 
749 /* Chip select base register */
750 #define MPI_CSBASE_REG(x)		(0x0 + (x) * 8)
751 #define MPI_CSBASE_BASE_SHIFT		13
752 #define MPI_CSBASE_BASE_MASK		(0x1ffff << MPI_CSBASE_BASE_SHIFT)
753 #define MPI_CSBASE_SIZE_SHIFT		0
754 #define MPI_CSBASE_SIZE_MASK		(0xf << MPI_CSBASE_SIZE_SHIFT)
755 
756 #define MPI_CSBASE_SIZE_8K		0
757 #define MPI_CSBASE_SIZE_16K		1
758 #define MPI_CSBASE_SIZE_32K		2
759 #define MPI_CSBASE_SIZE_64K		3
760 #define MPI_CSBASE_SIZE_128K		4
761 #define MPI_CSBASE_SIZE_256K		5
762 #define MPI_CSBASE_SIZE_512K		6
763 #define MPI_CSBASE_SIZE_1M		7
764 #define MPI_CSBASE_SIZE_2M		8
765 #define MPI_CSBASE_SIZE_4M		9
766 #define MPI_CSBASE_SIZE_8M		10
767 #define MPI_CSBASE_SIZE_16M		11
768 #define MPI_CSBASE_SIZE_32M		12
769 #define MPI_CSBASE_SIZE_64M		13
770 #define MPI_CSBASE_SIZE_128M		14
771 #define MPI_CSBASE_SIZE_256M		15
772 
773 /* Chip select control register */
774 #define MPI_CSCTL_REG(x)		(0x4 + (x) * 8)
775 #define MPI_CSCTL_ENABLE_MASK		(1 << 0)
776 #define MPI_CSCTL_WAIT_SHIFT		1
777 #define MPI_CSCTL_WAIT_MASK		(0x7 << MPI_CSCTL_WAIT_SHIFT)
778 #define MPI_CSCTL_DATA16_MASK		(1 << 4)
779 #define MPI_CSCTL_SYNCMODE_MASK		(1 << 7)
780 #define MPI_CSCTL_TSIZE_MASK		(1 << 8)
781 #define MPI_CSCTL_ENDIANSWAP_MASK	(1 << 10)
782 #define MPI_CSCTL_SETUP_SHIFT		16
783 #define MPI_CSCTL_SETUP_MASK		(0xf << MPI_CSCTL_SETUP_SHIFT)
784 #define MPI_CSCTL_HOLD_SHIFT		20
785 #define MPI_CSCTL_HOLD_MASK		(0xf << MPI_CSCTL_HOLD_SHIFT)
786 
787 /* PCI registers */
788 #define MPI_SP0_RANGE_REG		0x100
789 #define MPI_SP0_REMAP_REG		0x104
790 #define MPI_SP0_REMAP_ENABLE_MASK	(1 << 0)
791 #define MPI_SP1_RANGE_REG		0x10C
792 #define MPI_SP1_REMAP_REG		0x110
793 #define MPI_SP1_REMAP_ENABLE_MASK	(1 << 0)
794 
795 #define MPI_L2PCFG_REG			0x11C
796 #define MPI_L2PCFG_CFG_TYPE_SHIFT	0
797 #define MPI_L2PCFG_CFG_TYPE_MASK	(0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
798 #define MPI_L2PCFG_REG_SHIFT		2
799 #define MPI_L2PCFG_REG_MASK		(0x3f << MPI_L2PCFG_REG_SHIFT)
800 #define MPI_L2PCFG_FUNC_SHIFT		8
801 #define MPI_L2PCFG_FUNC_MASK		(0x7 << MPI_L2PCFG_FUNC_SHIFT)
802 #define MPI_L2PCFG_DEVNUM_SHIFT		11
803 #define MPI_L2PCFG_DEVNUM_MASK		(0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
804 #define MPI_L2PCFG_CFG_USEREG_MASK	(1 << 30)
805 #define MPI_L2PCFG_CFG_SEL_MASK		(1 << 31)
806 
807 #define MPI_L2PMEMRANGE1_REG		0x120
808 #define MPI_L2PMEMBASE1_REG		0x124
809 #define MPI_L2PMEMREMAP1_REG		0x128
810 #define MPI_L2PMEMRANGE2_REG		0x12C
811 #define MPI_L2PMEMBASE2_REG		0x130
812 #define MPI_L2PMEMREMAP2_REG		0x134
813 #define MPI_L2PIORANGE_REG		0x138
814 #define MPI_L2PIOBASE_REG		0x13C
815 #define MPI_L2PIOREMAP_REG		0x140
816 #define MPI_L2P_BASE_MASK		(0xffff8000)
817 #define MPI_L2PREMAP_ENABLED_MASK	(1 << 0)
818 #define MPI_L2PREMAP_IS_CARDBUS_MASK	(1 << 2)
819 
820 #define MPI_PCIMODESEL_REG		0x144
821 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK	(1 << 0)
822 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK	(1 << 1)
823 #define MPI_PCIMODESEL_EXT_ARB_MASK	(1 << 2)
824 #define MPI_PCIMODESEL_PREFETCH_SHIFT	4
825 #define MPI_PCIMODESEL_PREFETCH_MASK	(0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
826 
827 #define MPI_LOCBUSCTL_REG		0x14C
828 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK	(1 << 0)
829 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK	(1 << 1)
830 
831 #define MPI_LOCINT_REG			0x150
832 #define MPI_LOCINT_MASK(x)		(1 << (x + 16))
833 #define MPI_LOCINT_STAT(x)		(1 << (x))
834 #define MPI_LOCINT_DIR_FAILED		6
835 #define MPI_LOCINT_EXT_PCI_INT		7
836 #define MPI_LOCINT_SERR			8
837 #define MPI_LOCINT_CSERR		9
838 
839 #define MPI_PCICFGCTL_REG		0x178
840 #define MPI_PCICFGCTL_CFGADDR_SHIFT	2
841 #define MPI_PCICFGCTL_CFGADDR_MASK	(0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
842 #define MPI_PCICFGCTL_WRITEEN_MASK	(1 << 7)
843 
844 #define MPI_PCICFGDATA_REG		0x17C
845 
846 /* PCI host bridge custom register */
847 #define BCMPCI_REG_TIMERS		0x40
848 #define REG_TIMER_TRDY_SHIFT		0
849 #define REG_TIMER_TRDY_MASK		(0xff << REG_TIMER_TRDY_SHIFT)
850 #define REG_TIMER_RETRY_SHIFT		8
851 #define REG_TIMER_RETRY_MASK		(0xff << REG_TIMER_RETRY_SHIFT)
852 
853 
854 /*************************************************************************
855  * _REG relative to RSET_PCMCIA
856  *************************************************************************/
857 
858 #define PCMCIA_C1_REG			0x0
859 #define PCMCIA_C1_CD1_MASK		(1 << 0)
860 #define PCMCIA_C1_CD2_MASK		(1 << 1)
861 #define PCMCIA_C1_VS1_MASK		(1 << 2)
862 #define PCMCIA_C1_VS2_MASK		(1 << 3)
863 #define PCMCIA_C1_VS1OE_MASK		(1 << 6)
864 #define PCMCIA_C1_VS2OE_MASK		(1 << 7)
865 #define PCMCIA_C1_CBIDSEL_SHIFT		(8)
866 #define PCMCIA_C1_CBIDSEL_MASK		(0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
867 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK	(1 << 13)
868 #define PCMCIA_C1_EN_PCMCIA_MASK	(1 << 14)
869 #define PCMCIA_C1_EN_CARDBUS_MASK	(1 << 15)
870 #define PCMCIA_C1_RESET_MASK		(1 << 18)
871 
872 #define PCMCIA_C2_REG			0x8
873 #define PCMCIA_C2_DATA16_MASK		(1 << 0)
874 #define PCMCIA_C2_BYTESWAP_MASK		(1 << 1)
875 #define PCMCIA_C2_RWCOUNT_SHIFT		2
876 #define PCMCIA_C2_RWCOUNT_MASK		(0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
877 #define PCMCIA_C2_INACTIVE_SHIFT	8
878 #define PCMCIA_C2_INACTIVE_MASK		(0x3f << PCMCIA_C2_INACTIVE_SHIFT)
879 #define PCMCIA_C2_SETUP_SHIFT		16
880 #define PCMCIA_C2_SETUP_MASK		(0x3f << PCMCIA_C2_SETUP_SHIFT)
881 #define PCMCIA_C2_HOLD_SHIFT		24
882 #define PCMCIA_C2_HOLD_MASK		(0x3f << PCMCIA_C2_HOLD_SHIFT)
883 
884 
885 /*************************************************************************
886  * _REG relative to RSET_SDRAM
887  *************************************************************************/
888 
889 #define SDRAM_CFG_REG			0x0
890 #define SDRAM_CFG_ROW_SHIFT		4
891 #define SDRAM_CFG_ROW_MASK		(0x3 << SDRAM_CFG_ROW_SHIFT)
892 #define SDRAM_CFG_COL_SHIFT		6
893 #define SDRAM_CFG_COL_MASK		(0x3 << SDRAM_CFG_COL_SHIFT)
894 #define SDRAM_CFG_32B_SHIFT		10
895 #define SDRAM_CFG_32B_MASK		(1 << SDRAM_CFG_32B_SHIFT)
896 #define SDRAM_CFG_BANK_SHIFT		13
897 #define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
898 
899 #define SDRAM_MBASE_REG			0xc
900 
901 #define SDRAM_PRIO_REG			0x2C
902 #define SDRAM_PRIO_MIPS_SHIFT		29
903 #define SDRAM_PRIO_MIPS_MASK		(1 << SDRAM_PRIO_MIPS_SHIFT)
904 #define SDRAM_PRIO_ADSL_SHIFT		30
905 #define SDRAM_PRIO_ADSL_MASK		(1 << SDRAM_PRIO_ADSL_SHIFT)
906 #define SDRAM_PRIO_EN_SHIFT		31
907 #define SDRAM_PRIO_EN_MASK		(1 << SDRAM_PRIO_EN_SHIFT)
908 
909 
910 /*************************************************************************
911  * _REG relative to RSET_MEMC
912  *************************************************************************/
913 
914 #define MEMC_CFG_REG			0x4
915 #define MEMC_CFG_32B_SHIFT		1
916 #define MEMC_CFG_32B_MASK		(1 << MEMC_CFG_32B_SHIFT)
917 #define MEMC_CFG_COL_SHIFT		3
918 #define MEMC_CFG_COL_MASK		(0x3 << MEMC_CFG_COL_SHIFT)
919 #define MEMC_CFG_ROW_SHIFT		6
920 #define MEMC_CFG_ROW_MASK		(0x3 << MEMC_CFG_ROW_SHIFT)
921 
922 
923 /*************************************************************************
924  * _REG relative to RSET_DDR
925  *************************************************************************/
926 
927 #define DDR_DMIPSPLLCFG_REG		0x18
928 #define DMIPSPLLCFG_M1_SHIFT		0
929 #define DMIPSPLLCFG_M1_MASK		(0xff << DMIPSPLLCFG_M1_SHIFT)
930 #define DMIPSPLLCFG_N1_SHIFT		23
931 #define DMIPSPLLCFG_N1_MASK		(0x3f << DMIPSPLLCFG_N1_SHIFT)
932 #define DMIPSPLLCFG_N2_SHIFT		29
933 #define DMIPSPLLCFG_N2_MASK		(0x7 << DMIPSPLLCFG_N2_SHIFT)
934 
935 #define DDR_DMIPSPLLCFG_6368_REG	0x20
936 #define DMIPSPLLCFG_6368_P1_SHIFT	0
937 #define DMIPSPLLCFG_6368_P1_MASK	(0xf << DMIPSPLLCFG_6368_P1_SHIFT)
938 #define DMIPSPLLCFG_6368_P2_SHIFT	4
939 #define DMIPSPLLCFG_6368_P2_MASK	(0xf << DMIPSPLLCFG_6368_P2_SHIFT)
940 #define DMIPSPLLCFG_6368_NDIV_SHIFT	16
941 #define DMIPSPLLCFG_6368_NDIV_MASK	(0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
942 
943 #define DDR_DMIPSPLLDIV_6368_REG	0x24
944 #define DMIPSPLLDIV_6368_MDIV_SHIFT	0
945 #define DMIPSPLLDIV_6368_MDIV_MASK	(0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
946 
947 
948 /*************************************************************************
949  * _REG relative to RSET_M2M
950  *************************************************************************/
951 
952 #define M2M_RX				0
953 #define M2M_TX				1
954 
955 #define M2M_SRC_REG(x)			((x) * 0x40 + 0x00)
956 #define M2M_DST_REG(x)			((x) * 0x40 + 0x04)
957 #define M2M_SIZE_REG(x)			((x) * 0x40 + 0x08)
958 
959 #define M2M_CTRL_REG(x)			((x) * 0x40 + 0x0c)
960 #define M2M_CTRL_ENABLE_MASK		(1 << 0)
961 #define M2M_CTRL_IRQEN_MASK		(1 << 1)
962 #define M2M_CTRL_ERROR_CLR_MASK		(1 << 6)
963 #define M2M_CTRL_DONE_CLR_MASK		(1 << 7)
964 #define M2M_CTRL_NOINC_MASK		(1 << 8)
965 #define M2M_CTRL_PCMCIASWAP_MASK	(1 << 9)
966 #define M2M_CTRL_SWAPBYTE_MASK		(1 << 10)
967 #define M2M_CTRL_ENDIAN_MASK		(1 << 11)
968 
969 #define M2M_STAT_REG(x)			((x) * 0x40 + 0x10)
970 #define M2M_STAT_DONE			(1 << 0)
971 #define M2M_STAT_ERROR			(1 << 1)
972 
973 #define M2M_SRCID_REG(x)		((x) * 0x40 + 0x14)
974 #define M2M_DSTID_REG(x)		((x) * 0x40 + 0x18)
975 
976 #endif /* BCM63XX_REGS_H_ */
977