1 /* 2 * arch/arm/mach-vt8500/include/mach/vt8500_regs.h 3 * 4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 #ifndef __ASM_ARM_ARCH_VT8500_REGS_H 21 #define __ASM_ARM_ARCH_VT8500_REGS_H 22 23 /* VT8500 Registers Map */ 24 25 #define VT8500_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */ 26 #define VT8500_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */ 27 28 #define VT8500_DDR_BASE 0xd8000000 /* 1k DDR/DDR2 Memory 29 Controller */ 30 #define VT8500_DMA_BASE 0xd8001000 /* 1k DMA Controller */ 31 #define VT8500_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory 32 Controller */ 33 #define VT8500_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */ 34 #define VT8500_CIPHER_BASE 0xd8006000 /* 4k Cipher */ 35 #define VT8500_USB_BASE 0xd8007800 /* 2k USB OTG */ 36 # define VT8500_EHCI_BASE 0xd8007900 /* EHCI */ 37 # define VT8500_UHCI_BASE 0xd8007b01 /* UHCI */ 38 #define VT8500_PATA_BASE 0xd8008000 /* 512 PATA */ 39 #define VT8500_PS2_BASE 0xd8008800 /* 1k PS/2 */ 40 #define VT8500_NAND_BASE 0xd8009000 /* 1k NAND Controller */ 41 #define VT8500_NOR_BASE 0xd8009400 /* 1k NOR Controller */ 42 #define VT8500_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */ 43 #define VT8500_MS_BASE 0xd800b000 /* 1k MS/MSPRO Controller */ 44 #define VT8500_LCDC_BASE 0xd800e400 /* 1k LCD Controller */ 45 #define VT8500_VPU_BASE 0xd8050000 /* 256 VPU */ 46 #define VT8500_GOV_BASE 0xd8050300 /* 256 GOV */ 47 #define VT8500_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */ 48 #define VT8500_LCDF_BASE 0xd8050900 /* 256 LCD Formatter */ 49 #define VT8500_VID_BASE 0xd8050a00 /* 256 VID */ 50 #define VT8500_VPP_BASE 0xd8050b00 /* 256 VPP */ 51 #define VT8500_TSBK_BASE 0xd80f4000 /* 4k TSBK */ 52 #define VT8500_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */ 53 #define VT8500_JPEGENC_BASE 0xd80ff000 /* 4k JPEG Encoder */ 54 #define VT8500_RTC_BASE 0xd8100000 /* 64k RTC */ 55 #define VT8500_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */ 56 #define VT8500_SCC_BASE 0xd8120000 /* 64k System Configuration*/ 57 #define VT8500_PMC_BASE 0xd8130000 /* 64k PMC Configuration */ 58 #define VT8500_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/ 59 #define VT8500_UART0_BASE 0xd8200000 /* 64k UART 0 */ 60 #define VT8500_UART2_BASE 0xd8210000 /* 64k UART 2 */ 61 #define VT8500_PWM_BASE 0xd8220000 /* 64k PWM Configuration */ 62 #define VT8500_SPI0_BASE 0xd8240000 /* 64k SPI 0 */ 63 #define VT8500_SPI1_BASE 0xd8250000 /* 64k SPI 1 */ 64 #define VT8500_CIR_BASE 0xd8270000 /* 64k CIR */ 65 #define VT8500_I2C0_BASE 0xd8280000 /* 64k I2C 0 */ 66 #define VT8500_AC97_BASE 0xd8290000 /* 64k AC97 */ 67 #define VT8500_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */ 68 #define VT8500_UART1_BASE 0xd82b0000 /* 64k UART 1 */ 69 #define VT8500_UART3_BASE 0xd82c0000 /* 64k UART 3 */ 70 #define VT8500_PCM_BASE 0xd82d0000 /* 64k PCM */ 71 #define VT8500_I2C1_BASE 0xd8320000 /* 64k I2C 1 */ 72 #define VT8500_I2S_BASE 0xd8330000 /* 64k I2S */ 73 #define VT8500_ADC_BASE 0xd8340000 /* 64k ADC */ 74 75 #define VT8500_REGS_END_PHYS 0xd834ffff /* End of MMIO registers */ 76 #define VT8500_REGS_LENGTH (VT8500_REGS_END_PHYS \ 77 - VT8500_REGS_START_PHYS + 1) 78 79 #endif 80